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/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
11 #define MTK_DP_HPD_DISCONNECT BIT(1)
12 #define MTK_DP_HPD_CONNECT BIT(2)
13 #define MTK_DP_HPD_INTERRUPT BIT(3)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
[all …]
/linux/include/soc/mscc/
H A Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
[all …]
H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
[all …]
/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
219 #define RCC_SECCFGR_PLL12SEC 8
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
245 #define RCC_MP_APRSTCR_RSTTO_MASK GENMASK(14, 8)
246 #define RCC_MP_APRSTCR_RSTTO_SHIFT 8
249 #define RCC_MP_APRSTSR_RSTTOV_MASK GENMASK(14, 8)
250 #define RCC_MP_APRSTSR_RSTTOV_SHIFT 8
[all …]
/linux/drivers/net/ethernet/asix/
H A Dax88796c_main.h1 /* SPDX-License-Identifier: GPL-2.0-only */
31 #define AX_MCAST_FILTER_SIZE 8
121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
123 #define AX_FC_ANEG BIT(2)
126 #define AX_CAP_COMP BIT(0)
153 #define PSR_DEV_READY BIT(7)
155 #define PSR_RESET_CLR BIT(15)
158 #define FER_IPALM BIT(0)
159 #define FER_DCRC BIT(1)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_regs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
[all …]
/linux/drivers/pmdomain/mediatek/
H A Dmt6893-pm-domains.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/power/mediatek,mt6893-power.h>
12 #include "mtk-pm-domains.h"
27 #define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(7)
29 #define MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(24)
30 #define MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(25)
31 #define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(6)
32 #define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(7)
33 #define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1 BIT(26)
34 #define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2 BIT(0)
[all …]
/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
24 WARN_ON(!FIELD_FIT(hvs->vc4->gen == VC4_GEN_6_C ? \
27 FIELD_PREP(hvs->vc4->gen == VC4_GEN_6_C ? \
32 #define VC6_GET_FIELD(word, field) FIELD_GET(hvs->vc4->gen == VC4_GEN_6_C ? \
40 ('3' << 8) | \
51 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
52 # define V3D_IDENT1_QUPS_SHIFT 8
61 # define V3D_L2CACTL_L2CCLR BIT(2)
62 # define V3D_L2CACTL_L2CDIS BIT(1)
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
19 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
27 #define MT_EFUSE_CTRL_KICK BIT(30)
28 #define MT_EFUSE_CTRL_SEL BIT(31)
34 #define MT_COEXCFG0_COEX_EN BIT(0)
37 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
38 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
39 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
[all …]
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
32 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
[all …]
H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
41 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
[all …]
/linux/drivers/staging/vme_user/
H A Dvme_tsi148.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 #define TSI148_MAX_MASTER 8 /* Max Master Windows */
27 #define TSI148_MAX_SLAVE 8 /* Max Slave Windows */
30 #define TSI148_MAX_SEMAPHORE 8 /* Max Semaphores */
50 * Layout of a DMAC Linked-List Descriptor
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
79 * TSI148 ASIC register structure overlays and bit field definitions.
83 * PCFS - PCI Configuration Space Registers
84 * LCSR - Local Control and Status Registers
[all …]
/linux/sound/soc/codecs/
H A Dmt6357.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt6357.h -- mt6357 ALSA SoC audio codec driver
14 /* Reg bit defines */
16 #define MT6357_GPIO8_DIR_MASK BIT(8)
18 #define MT6357_GPIO8_DIR_OUTPUT BIT(8)
19 #define MT6357_GPIO9_DIR_MASK BIT(9)
21 #define MT6357_GPIO9_DIR_OUTPUT BIT(9)
22 #define MT6357_GPIO10_DIR_MASK BIT(10)
24 #define MT6357_GPIO10_DIR_OUTPUT BIT(10)
25 #define MT6357_GPIO11_DIR_MASK BIT(11)
[all …]
/linux/drivers/clk/renesas/
H A Dr9a09g056-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
68 {3, 8},
75 {2, 8},
83 {2, 8},
130 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
136 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
173 BUS_MSTOP(3, BIT(5))),
[all …]
H A Dr9a09g047-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
73 {3, 8},
86 {2, 8},
94 {2, 8},
142 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
149 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
190 BUS_MSTOP(5, BIT(9))),
[all …]
H A Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
76 {3, 8},
89 {2, 8},
97 {2, 8},
145 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
151 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
197 BUS_MSTOP(5, BIT(9))),
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
38 #define PDN_DAC_MASK_SFT BIT(25)
[all …]
/linux/drivers/media/cec/platform/tegra/
H A Dtegra_cec.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved.
11 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
37 #define TEGRA_CEC_HWCTRL_RX_SNOOP BIT(15)
38 #define TEGRA_CEC_HWCTRL_RX_NAK_MODE BIT(16)
39 #define TEGRA_CEC_HWCTRL_TX_NAK_MODE BIT(24)
40 #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE BIT(30)
41 #define TEGRA_CEC_HWCTRL_TX_RX_MODE BIT(31)
43 #define TEGRA_CEC_INPUT_FILTER_MODE BIT(31)
47 #define TEGRA_CEC_TX_REG_EOM BIT(8)
[all …]
/linux/Documentation/gpu/
H A Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
50 * Component 1: G(8)
[all …]
/linux/include/sound/
H A Dump_msg.h1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /* MIDI 1.0 / 2.0 Status Code (4bit) */
27 /* MIDI 1.0 Channel Control (7bit) */
36 UMP_CC_BALANCE = 8,
128 /* MIDI 1.0 Note Off / Note On (32bit) */
135 u32 note:8;
136 u32 velocity:8;
138 u32 velocity:8;
139 u32 note:8;
147 /* MIDI 1.0 Poly Pressure (32bit) */
[all …]
/linux/drivers/media/platform/ti/omap3isp/
H A Dispreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Registers definitions
48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
66 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
[all …]

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