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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,ipq5332-usb-hsphy.yaml49 usb-phy@7b000 {
/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts58 interrupt-map-mask = <0x1800 0 0 7>;
104 mmc@b000 {
H A Darm-realview-eb.dtsi105 reg-io-width = <7>;
224 led@8,7 {
229 label = "versatile:7";
344 serial2: serial@1000b000 {
H A Dvexpress-v2m.dtsi39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
86 <7 0 0x10000000 0x00020000>;
123 iofpga@7,00000000 {
127 ranges = <0 7 0 0x20000>;
235 v2m_serial2: serial@b000 {
238 interrupts = <7>;
430 gpios = <&v2m_led_gpios 7 0>;
489 arm,vexpress-sysreg,func = <7 0>;
/linux/drivers/gpu/drm/meson/
H A Dmeson_dw_hdmi.h15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
39 * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable
61 * [ 7] rxsense_fall starting from G12A
76 * Bit 7 RW rxsense_fall starting from G12A
86 * [7] rxsense_fall starting from G12A
101 #define HDMITX_TOP_INTR_RXSENSE_FALL BIT(7)
104 * Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
107 * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3620.dtsi149 interrupts = <0 6 4>, <0 7 4>;
227 &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
242 &pmx0 6 5 1 &pmx0 7 6 1>;
255 gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
257 &pmx0 6 3 1 &pmx0 7 3 1>;
272 &pmx0 6 11 1 &pmx0 7 11 1>;
287 &pmx0 6 13 1 &pmx0 7 13 1>;
294 gpio5: gpio@80b000 {
302 &pmx0 6 16 1 &pmx0 7 16 1>;
317 &pmx0 6 18 1 &pmx0 7 19 1>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx27.dtsi180 uart2: serial@1000b000 {
275 dmas = <&dma 7>;
404 uart5: serial@1001b000 {
550 fec: ethernet@1002b000 {
/linux/drivers/hwmon/pmbus/
H A Dmp9941.c59 * page = 0, MFR_RESO_SET[7:6] defines the vout format in mp9941_set_vout_format()
62 ret = (ret & ~GENMASK(7, 6)) | FIELD_PREP(GENMASK(7, 6), 3); in mp9941_set_vout_format()
114 * 3'b000 set the iout scale as 0.5A/Lsb in mp9941_identify_iin_scale()
174 ret = DIV_ROUND_CLOSEST((ret & GENMASK(7, 0)) * MP9941_VIN_LIMIT_UINT, in mp9941_read_word_data()
182 ret = ret & GENMASK(7, 0); in mp9941_read_word_data()
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8536ds.dtsi71 partition@7f00000 {
76 partition@7f80000 {
240 usb@2b000 {
H A Dmpc8536si-post.dtsi70 interrupt-map-mask = <0xf800 0 0 7>;
99 interrupt-map-mask = <0xf800 0 0 7>;
127 interrupt-map-mask = <0xf800 0 0 7>;
235 usb@2b000 {
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044.dtsi48 interrupt-map-mask = <0 0 0 7>;
83 interrupt-map-mask = <0 0 0 7>;
118 interrupt-map-mask = <0 0 0 7>;
153 interrupt-map-mask = <0 0 0 7>;
188 interrupt-map-mask = <0 0 0 7>;
256 snps,priority = <0 1 2 3 4 5 6 7>;
399 sd: mmc@703000b000 {
513 gpio2: gpio@704000b000 {
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8365-pinctrl.yaml143 7: (E1, E0, EN) = (1, 1, 1)
144 So the valid arguments are from 0 to 7.
146 enum: [0, 1, 2, 3, 4, 5, 6, 7]
212 pio: pinctrl@1000b000 {
/linux/include/linux/irqchip/
H A Darm-gic-v5.h69 #define GICV5_IRS_IDR1_PRIORITY_BITS_1BITS 0b000
102 #define GICV5_IRS_CR1_IST_WA BIT(7)
129 #define GICV5_IRS_IST_CFGR_ISTSZ GENMASK(8, 7)
171 #define GICV5_ITS_IDR1_ITT_LEVELS BIT(7)
185 #define GICV5_ITS_CR1_ITT_RA BIT(7)
192 #define GICV5_ITS_DT_CFGR_L2SZ GENMASK(7, 6)
/linux/arch/arm64/boot/dts/realtek/
H A Drtd16xx.dtsi113 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
171 misc: syscon@1b000 {
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm53573.dtsi102 <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
244 gmac1: ethernet@b000 {
/linux/arch/arm64/boot/dts/marvell/mmp/
H A Dpxa1908.dtsi128 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
204 pinctrl-single,function-mask = <7>;
230 apbcp: clock-controller@3b000 {
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-beagle-xm.dts154 etb@5401b000 {
281 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
331 * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
/linux/Documentation/arch/powerpc/
H A Dtransactional_memory.rst191 These can be checked by the user program's abort handler as TEXASR[0:7]. If
192 bit 7 is set, it indicates that the error is considered persistent. For example
269 if (MSR 29:31 ¬ = 0b010 | SRR1 29:31 ¬ = 0b000) then
/linux/Documentation/arch/arm/pxa/
H A Dmfp.rst160 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
169 Bit 7: SLEEP_OE_N - enable outputs during low power modes
177 Bit 0 - 2: AF_SEL - alternate function selection, 8 possibilities, from 0-7
179 0b000 - fast 1mA
/linux/drivers/input/touchscreen/
H A Diqs5xx.c40 #define IQS5XX_SHOW_RESET BIT(7)
41 #define IQS5XX_ACK_RESET BIT(7)
565 * A000 and B000 devices use 8-bit and 16-bit addressing, respectively. in iqs5xx_dev_init()
588 * B000 device via new firmware. in iqs5xx_dev_init()
/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c318 4, 5, 6, 7, 8, 9, 10, 14, in get_sys_div_x2()
339 /* 0b000 is "times 36" */ in get_cpmf_mult_x2()
340 72, 2, 2, 3, 4, 5, 6, 7, in get_cpmf_mult_x2()
343 /* 0b000 is "bypass" */ in get_cpmf_mult_x2()
344 2, 2, 2, 3, 4, 5, 6, 7, in get_cpmf_mult_x2()
569 MCLK_SETUP_DATA_PSC(7),
693 mccr_reg, 7, 1); in mpc512x_clk_setup_mclk()
750 * allow to setup the divider's bits 7:1, which results in that in mpc512x_clk_setup_clock_tree()
758 &clkregs->scfr2, 1, 7, in mpc512x_clk_setup_clock_tree()
763 9, 7, CLK_DIVIDER_ONE_BASED); in mpc512x_clk_setup_clock_tree()
[all …]
/linux/arch/arm64/tools/
H A Dsysreg93 Res0 11:7
266 UnsignedEnum 7:6 P3
318 Field 7:0 Aff0
321 Sysreg SPMCFGR_EL1 2 0 9 13 7
336 Field 7:0 N
347 Sysreg PMCCNTSVR_EL1 2 0 14 11 7
361 Res0 7:5
395 Sysreg SPMSCR_EL1 2 7 9 14 7
434 UnsignedEnum 7:4 State1
474 Enum 7:4 Security
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi507 thermal: thermal@1100b000 {
829 interrupt-map-mask = <0 0 0 7>;
867 interrupt-map-mask = <0 0 0 7>;
957 wed1: wed@1020b000 {
/linux/net/dsa/
H A Dtag_brcm.c63 #define BRCM_IG_TS_SHIFT 7
159 /* The opcode should never be different than 0b000 */ in brcm_tag_rcv_ll()
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi224 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
225 <&cpu1_intc 3>, <&cpu1_intc 7>,
226 <&cpu2_intc 3>, <&cpu2_intc 7>,
227 <&cpu3_intc 3>, <&cpu3_intc 7>,
228 <&cpu4_intc 3>, <&cpu4_intc 7>;
249 interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
410 i2c1: i2c@2010b000 {

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