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/linux/tools/arch/x86/kcpuid/
H A Dcpuid.csv1 # SPDX-License-Identifier: CC0-1.0
2 # Generator: x86-cpuid-db v2.4
5 # Auto-generated file.
6 # Please submit all updates and bugfixes to https://x86-cpuid.org
15 0x0, 0, eax, 31:0, max_std_leaf , Highest standard CPUID leaf supported
16 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 -
[all...]
/linux/arch/alpha/include/asm/
H A Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
63 ldq $7,24($18) \n\
73 xor $0,$1,$0 # 7 cycles from $1 load \n\
81 xor $6,$7,$6 \n\
117 ldq $7,16($18) \n\
132 xor $6,$7,$7 # 6 cycles from $7 load \n\
141 xor $7,$20,$20 # 7 cycles from $20 load \n\
143 xor $22,$23,$23 # 7 cycles from $23 load \n\
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
[all …]
/linux/lib/crypto/powerpc/
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
[all …]
H A Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
84 std 31,136(1)
87 ld 7,0(4)
93 mulld 22,7,6
[all …]
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
14 # 4. c += d; b ^= c; b <<<= 7
19 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 7
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
78 stdu 1,-752(1)
97 SAVE_GPR 31, 248, 1
111 SAVE_VRS 31, 176, 9
130 SAVE_VSX 31, 464, 9
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v3.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
18 /* Bits 5-31 reserved */
31 [CLKON_HPS] = BIT(7),
41 /* Bits 17-31 reserved */
50 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
52 /* Bits 22-23 reserved */
54 /* Bits 25-31 reserved */
61 [MEM_BADDR] = GENMASK(31, 16),
68 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
[all …]
H A Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
13 [MAX_PIPES] = GENMASK(7, 0),
16 [PROD_LOWEST] = GENMASK(31, 24),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
39 /* Bits 17-18 reserved */
44 /* Bits 28-29 reserved */
46 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
59 [CLKON_HPS] = BIT(7),
83 [DRBIP] = BIT(31),
[all …]
H A Dipa_reg-v5.0.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
13 [MAX_PIPES] = GENMASK(7, 0),
16 [PROD_LOWEST] = GENMASK(31, 24),
29 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
45 /* Bits 28-29 reserved */
47 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
60 [CLKON_HPS] = BIT(7),
84 [DRBIP] = BIT(31),
90 [ROUTE_DEF_PIPE] = GENMASK(7, 0),
[all …]
H A Dipa_reg-v4.2.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
31 /* Bits 21-31 reserved */
44 [CLKON_HPS] = BIT(7),
67 /* Bits 30-31 reserved */
76 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
78 /* Bits 22-23 reserved */
80 /* Bits 25-31 reserved */
87 [MEM_BADDR] = GENMASK(31, 16),
[all …]
H A Dipa_reg-v4.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
32 /* Bits 22-31 reserved */
45 [CLKON_HPS] = BIT(7),
69 /* Bit 31 reserved */
78 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
80 /* Bits 22-23 reserved */
82 /* Bits 25-31 reserved */
89 [MEM_BADDR] = GENMASK(31, 16),
[all …]
H A Dipa_reg-v3.5.1.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
18 /* Bits 5-31 reserved */
31 [CLKON_HPS] = BIT(7),
46 /* Bits 22-31 reserved */
55 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
57 /* Bits 22-23 reserved */
59 /* Bits 25-31 reserved */
66 [MEM_BADDR] = GENMASK(31, 16),
73 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
[all …]
H A Dipa_reg-v4.11.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
36 /* Bits 24-29 reserved */
38 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
51 [CLKON_HPS] = BIT(7),
75 [DRBIP] = BIT(31),
84 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
86 /* Bits 22-23 reserved */
88 /* Bits 25-31 reserved */
[all …]
H A Dipa_reg-v4.7.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
32 /* Bits 22-31 reserved */
45 [CLKON_HPS] = BIT(7),
69 [DRBIP] = BIT(31),
78 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
80 /* Bits 22-23 reserved */
82 /* Bits 25-31 reserved */
89 [MEM_BADDR] = GENMASK(31, 16),
[all …]
H A Dipa_reg-v4.9.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2022-2024 Linaro Ltd. */
20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7),
35 /* Bits 25-29 reserved */
37 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
50 [CLKON_HPS] = BIT(7),
74 [DRBIP] = BIT(31),
83 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
85 /* Bits 22-23 reserved */
87 /* Bits 25-31 reserved */
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
24 PKT_TYPE_RX_EVENT = 7,
27 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
33 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
59 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
70 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
72 #define MT_RXV1_VHTA1_B5_B4 GENMASK(31, 30)
[all …]
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18)
19 #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19)
46 #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
51 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
58 #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28)
127 #define MT_PSE_RTA_REDIRECT_EN BIT(7)
130 #define MT_PSE_RTA_BUSY BIT(31)
143 #define MT_AGC_41_RSSI_1 GENMASK(7, 0)
164 #define MT_PHYCTRL_2_STATUS_EN BIT(7)
[all …]
/linux/tools/testing/selftests/hid/tests/
H A Dtest_multitouch.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
20 KERNEL_MODULE = base.KernelModule("hid-multitouch", "hid_multitouch")
35 "CONFIDENCE": BIT(7),
302 Report Size (7)
310 Unit Exponent (-1)
335 Unit Exponent (-4)
370 Report Size (7)
378 Unit Exponent (-1)
397 Unit Exponent (-4)
[all …]
/linux/arch/arm64/tools/
H A Dsysreg1 # SPDX-License-Identifier: GPL-2.0-only
52 # NI - Not implemented
53 # IMP - Implemented
61 Field 31:0 DTRRX
65 Res0 63:31
77 Field 31 TFO
93 Res0 11:7
101 Field 31:0 DTRTX
112 Field 31:0 OPCODE
117 Field 31:0 EDECCR
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
22 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
31 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
59 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
70 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
75 #define MT_RXD6_QOS_CTL GENMASK(31, 16)
77 #define MT_RXD7_HT_CONTROL GENMASK(31, 0)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD0_Q_IDX GENMASK(31, 25)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
67 #define MT_TXD2_FIX_RATE BIT(31)
78 #define MT_TXD2_NDPA BIT(7)
83 #define MT_TXD3_SN_VALID BIT(31)
97 #define MT_TXD4_PN_LOW GENMASK(31, 0)
99 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
105 #define MT_TXD5_PID GENMASK(7, 0)
[all …]
/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
54 以下示例介绍了打包u64字段的内存布局。打包缓冲区中的字节偏移量始终默认为0，1...7。
62 7 6 5 4
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
[all …]
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h1 /* SPDX-License-Identifier: GPL-2.0 */
72 * DF2 DstFabricID [7:0]
82 #define DF2_DST_FABRIC_ID GENMASK(7, 0)
161 * DF2 DramBaseAddr [31:12]
162 * DF3 DramBaseAddr [31:12]
163 * DF3p5 DramBaseAddr [31:12]
171 #define DF2_BASE_ADDR GENMASK(31, 12)
183 * DF2 DramHoleBase [31:24]
184 * DF3 DramHoleBase [31:24]
185 * DF3p5 DramHoleBase [31:24]
[all …]
/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl502d.h2 * Copyright (c) 2003 - 2004, NVIDIA CORPORATION. All rights reserved.
30 …_WAIT_FOR_IDLE_V 31:0
33 …_SET_DST_CONTEXT_DMA_HANDLE 31:0
36 …_SET_SRC_CONTEXT_DMA_HANDLE 31:0
39 …_SET_SEMAPHORE_CONTEXT_DMA_HANDLE 31:0
42 …_SET_DST_FORMAT_V 7:0
78 …_SET_DST_PITCH_V 31:0
81 …_SET_DST_WIDTH_V 31:0
84 …_SET_DST_HEIGHT_V 31:0
87 …_SET_DST_OFFSET_UPPER_V 7:0
[all …]
H A Dcl5039.h2 * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved.
30 …_NO_OPERATION_V 31:0
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
39 …_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0
49 …_SET_SRC_BLOCK_SIZE_HEIGHT 7:4
65 …_SET_SRC_WIDTH_V 31:0
68 …_SET_SRC_HEIGHT_V 31:0
71 …_SET_SRC_DEPTH_V 31:0
74 …_SET_SRC_LAYER_V 31:0
[all …]

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