Lines Matching +full:7 +full:- +full:31
1 /* SPDX-License-Identifier: GPL-2.0 */
72 * DF2 DstFabricID [7:0]
82 #define DF2_DST_FABRIC_ID GENMASK(7, 0)
161 * DF2 DramBaseAddr [31:12]
162 * DF3 DramBaseAddr [31:12]
163 * DF3p5 DramBaseAddr [31:12]
171 #define DF2_BASE_ADDR GENMASK(31, 12)
183 * DF2 DramHoleBase [31:24]
184 * DF3 DramHoleBase [31:24]
185 * DF3p5 DramHoleBase [31:24]
188 * DF4 DramHoleBase [31:24]
189 * DF4p5 DramHoleBase [31:24]
191 #define DF_DRAM_HOLE_BASE_MASK GENMASK(31, 24)
202 * DF2 DramLimitAddr [31:12]
203 * DF3 DramLimitAddr [31:12]
204 * DF3p5 DramLimitAddr [31:12]
212 #define DF2_DRAM_LIMIT_ADDR GENMASK(31, 12)
240 * DF4p5 HashIntlvCtl4K [7]
252 #define DF4p5_HASH_CTL_4K BIT(7)
264 * DF2 HiAddrOffset [31:20]
265 * DF3 HiAddrOffset [31:12]
266 * DF3p5 HiAddrOffset [31:12]
271 * MI300 HiAddrOffset [31:1]
273 #define DF2_HI_ADDR_OFFSET GENMASK(31, 20)
274 #define DF3_HI_ADDR_OFFSET GENMASK(31, 12)
277 #define DF4_HI_ADDR_OFFSET GENMASK(31, 1)
330 * DF2 IntLvNumChan [7:4]
340 #define DF2_INTLV_NUM_CHAN GENMASK(7, 4)
358 * DF3 IntLvNumDies [7:6]
359 * DF3p5 IntLvNumDies [7]
368 #define DF3_INTLV_NUM_DIES GENMASK(7, 6)
369 #define DF3p5_INTLV_NUM_DIES BIT(7)
427 * D18F2x90 [Non-power-of-2 channel Configuration Register for COH_ST DRAM Address Maps]
486 * DF3p5 NodeIdMask [31:16]
489 * DF4 NodeIdMask [31:16]
490 * DF4p5 NodeIdMask [31:16]
493 #define DF4_NODE_ID_MASK GENMASK(31, 16)
550 * DF4 RemapSel [7:5]
555 #define DF4_REMAP_SEL GENMASK(7, 5)
573 * DF3p5 SocketIdMask [31:16]
576 * DF4 SocketIdMask [31:16]
577 * DF4p5 SocketIdMask [31:16]
581 #define DF4_SOCKET_ID_MASK GENMASK(31, 16)
592 * DF2 SocketIdShift [31:28]
604 #define DF2_SOCKET_ID_SHIFT GENMASK(31, 28)