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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dmmintrin.h27 __min_vector_width__(64)))
42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
59 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
67 /// A 64-bit integer vector.
68 /// \returns A 32-bit signed integer value containing the lower 32 bits of the
76 /// Casts a 64-bit signed integer value into a 64-bit integer vector.
83 /// A 64-bit signed integer.
[all …]
H A Dfmaintrin.h21 /// Computes a multiply-add of 128-bit vectors of [4 x float].
29 /// A 128-bit vector of [4 x float] containing the multiplicand.
31 /// A 128-bit vector of [4 x float] containing the multiplier.
33 /// A 128-bit vector of [4 x float] containing the addend.
34 /// \returns A 128-bit vector of [4 x float] containing the result.
41 /// Computes a multiply-add of 128-bit vectors of [2 x double].
49 /// A 128-bit vector of [2 x double] containing the multiplicand.
51 /// A 128-bit vector of [2 x double] containing the multiplier.
53 /// A 128-bit vector of [2 x double] containing the addend.
54 /// \returns A 128-bit [2 x double] vector containing the result.
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H A Dbmi2intrin.h20 /// Copies the unsigned 32-bit integer \a __X and zeroes the upper bits
21 /// starting at bit number \a __Y.
36 /// The 32-bit source value to copy.
38 /// The lower 8 bits specify the bit number of the lowest bit to zero.
39 /// \returns The partially zeroed 32-bit value.
46 /// Deposit (scatter) low-order bits from the unsigned 32-bit integer \a __X
47 /// into the 32-bit result, according to the mask in the unsigned 32-bit
66 /// The 32-bit source value to copy.
68 /// The 32-bit mask specifying where to deposit source bits.
69 /// \returns The 32-bit result.
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H A Dtmmintrin.h22 __target__("ssse3,no-evex512"), __min_vector_width__(64)))
26 __min_vector_width__(64)))
28 /// Computes the absolute value of each of the packed 8-bit signed
29 /// integers in the source operand and stores the 8-bit unsigned integer
37 /// A 64-bit vector of [8 x i8].
38 /// \returns A 64-bit integer vector containing the absolute values of the
46 /// Computes the absolute value of each of the packed 8-bit signed
47 /// integers in the source operand and stores the 8-bit unsigned integer
55 /// A 128-bit vector of [16 x i8].
56 /// \returns A 128-bit integer vector containing the absolute values of the
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H A Demmintrin.h57 __target__("mmx,sse2,no-evex512"), __min_vector_width__(64)))
60 /// sum in the lower 64 bits of the result. The upper 64 bits of the result
68 /// A 128-bit vector of [2 x double] containing one of the source operands.
70 /// A 128-bit vector of [2 x double] containing one of the source operands.
71 /// \returns A 128-bit vector of [2 x double] whose lower 64 bits contain the
72 /// sum of the lower 64 bits of both operands. The upper 64 bits are copied
73 /// from the upper 64 bits of the first source operand.
80 /// Adds two 128-bit vectors of [2 x double].
87 /// A 128-bit vector of [2 x double] containing one of the source operands.
89 /// A 128-bit vector of [2 x double] containing one of the source operands.
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H A Dbmiintrin.h29 /// An unsigned 16-bit integer whose trailing zeros are to be counted.
30 /// \returns An unsigned 16-bit integer containing the number of trailing zero
50 /// An unsigned 16-bit integer whose trailing zeros are to be counted.
51 /// \returns An unsigned 16-bit integer containing the number of trailing zero
63 /// An unsigned 32-bit integer whose trailing zeros are to be counted.
64 /// \returns An unsigned 32-bit integer containing the number of trailing zero
80 /// An unsigned 32-bit integer whose trailing zeros are to be counted.
81 /// \returns A 32-bit integer containing the number of trailing zero bits in
101 /// An unsigned 32-bit integer whose trailing zeros are to be counted.
102 /// \returns An unsigned 32-bit integer containing the number of trailing zero
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H A Draointintrin.h20 /// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B,
31 /// A pointer to a 32-bit memory location.
33 /// A 32-bit integer value.
42 /// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B,
53 /// A pointer to a 32-bit memory location.
55 /// A 32-bit integer value.
64 /// Atomically or a 32-bit value at memory operand \a __A and a 32-bit \a __B,
75 /// A pointer to a 32-bit memory location.
77 /// A 32-bit integer value.
86 /// Atomically xor a 32-bit value at memory operand \a __A and a 32-bit \a __B,
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H A Dia32intrin.h29 /// Finds the first set bit starting from the least significant bit. The result
38 /// A 32-bit integer operand.
39 /// \returns A 32-bit integer containing the bit number.
46 /// Finds the first set bit starting from the most significant bit. The result
55 /// A 32-bit integer operand.
56 /// \returns A 32-bit integer containing the bit number.
71 /// A 32-bit integer operand.
72 /// \returns A 32-bit integer containing the swapped bytes.
86 /// A 32-bit integer operand.
87 /// \returns A 32-bit integer containing the swapped bytes.
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H A Dxmmintrin.h40 __target__("mmx,sse,no-evex512"), __min_vector_width__(64)))
42 /// Adds the 32-bit float values in the low-order bits of the operands.
49 /// A 128-bit vector of [4 x float] containing one of the source operands.
52 /// A 128-bit vector of [4 x float] containing one of the source operands.
54 /// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the sum
64 /// Adds two 128-bit vectors of [4 x float], and returns the results of
72 /// A 128-bit vector of [4 x float] containing one of the source operands.
74 /// A 128-bit vector of [4 x float] containing one of the source operands.
75 /// \returns A 128-bit vector of [4 x float] containing the sums of both
83 /// Subtracts the 32-bit float value in the low-order bits of the second
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H A Davxifmaintrin.h27 /// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
28 /// and \a __Z to form a 104-bit intermediate result. Add the high 52-bit
30 /// unsigned 64-bit integer in \a __X, and store the results in \a dst.
44 /// A 128-bit vector of [2 x i64]
46 /// A 128-bit vector of [2 x i64]
48 /// A 128-bit vector of [2 x i64]
52 /// i := j*64
64 /// Multiply packed unsigned 52-bit integers in each 64-bit element of \a __Y
65 /// and \a __Z to form a 104-bit intermediate result. Add the high 52-bit
67 /// unsigned 64-bit integer in \a __X, and store the results in \a dst.
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/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_ia32cap.374 stored internally as ten 32\-bit capability vectors and for simplicity
75 represented logically below as five 64\-bit vectors. This logical
81 environment variable capability bit modifications are applied. After toolkit
94 .IP "bit #0+4 denoting presence of Time-Stamp Counter;" 4
95 .IX Item "bit #0+4 denoting presence of Time-Stamp Counter;"
97 .IP "bit #0+19 denoting availability of CLFLUSH instruction;" 4
98 .IX Item "bit #0+19 denoting availability of CLFLUSH instruction;"
99 .IP "bit #0+20, reserved by Intel, is used to choose among RC4 code paths;" 4
100 .IX Item "bit #0+20, reserved by Intel, is used to choose among RC4 code paths;"
101 .IP "bit #0+23 denoting MMX support;" 4
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/freebsd/contrib/file/magic/Magdir/
H A Dmach9 # if set, it's for the 64-bit version of the architecture
10 # yes, this is separate from the low-order magic number bit
11 # it's also separate from the "64-bit libraries" bit in the
20 # 32-bit ABIs.
153 # 64-bit ABIs.
155 >>0 belong&0x00ffffff 0 64-bit architecture=%d
156 >>0 belong&0x00ffffff 1 64-bit architecture=%d
157 >>0 belong&0x00ffffff 2 64-bit architecture=%d
158 >>0 belong&0x00ffffff 3 64-bit architecture=%d
159 >>0 belong&0x00ffffff 4 64-bit architecture=%d
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H A Ddyadic21 >>>1 byte 0x01 component file 32-bit non-journaled non-checksummed
27 >>>>7 byte&0x28 0x00 32-bit
28 >>>>7 byte&0x28 0x20 64-bit
36 >>>1 byte 0x08 mapped file 32-bit
37 >>>1 byte 0x09 component file 64-bit non-journaled non-checksummed
38 >>>1 byte 0x0a mapped file 64-bit
39 >>>1 byte 0x0b component file 32-bit level 1 journaled non-checksummed
40 >>>1 byte 0x0c component file 64-bit level 1 journaled non-checksummed
41 >>>1 byte 0x0d component file 32-bit level 1 journaled checksummed
42 >>>1 byte 0x0e component file 64-bit level 1 journaled checksummed
[all …]
/freebsd/crypto/openssl/doc/man3/
H A DOPENSSL_ia32cap.pod15 stored internally as ten 32-bit capability vectors and for simplicity
16 represented logically below as five 64-bit vectors. This logical
22 environment variable capability bit modifications are applied. After toolkit
39 =item bit #0+4 denoting presence of Time-Stamp Counter;
41 =item bit #0+19 denoting availability of CLFLUSH instruction;
43 =item bit #0+20, reserved by Intel, is used to choose among RC4 code paths;
45 =item bit #0+23 denoting MMX support;
47 =item bit #0+24, FXSR bit, denoting availability of XMM registers;
49 =item bit #0+25 denoting SSE support;
51 =item bit #0+26 denoting SSE2 support;
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/freebsd/sys/contrib/openzfs/config/
H A Dhost-cpu-c-abi.m424 dnl contains 32-bit instructions, whereas 'sparc64' code contains 64-bit
25 dnl instructions. A process on a SPARC CPU can be in 32-bit mode or in 64-bit
66 # - 64-bit instruction set, 64-bit pointers, 64-bit 'long': x86_64.
67 # - 64-bit instruction set, 64-bit pointers, 32-bit 'long': x86_64
69 # - 64-bit instruction set, 32-bit pointers, 32-bit 'long': x86_64-x32.
70 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': i386.
103 # - aarch64 instruction set, 64-bit pointers, 64-bit 'long': arm64.
104 # - aarch64 instruction set, 32-bit pointers, 32-bit 'long': arm64-ilp32.
105 # - 32-bit instruction set, 32-bit pointers, 32-bit 'long': arm or armhf.
148 # On hppa, the C compiler may be generating 32-bit code or 64-bit
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/freebsd/sys/contrib/edk2/Include/Library/
H A DBaseLib.h145 // Bit shifts for the ID_AA64ISAR0_EL1 register.
163 // Bit masks for the ID_AA64ISAR0_EL1 fields.
181 // Bit masks for the ID_AA64ISAR0_EL1 field values.
400 @param Needs to enable local interrupt bit.
410 @param Needs to disable local interrupt bit.
609 If String is not aligned on a 16-bit boundary, then ASSERT().
634 If String is not aligned on a 16-bit boundary, then ASSERT().
661 If Destination is not aligned on a 16-bit boundary, then ASSERT().
662 If Source is not aligned on a 16-bit boundary, then ASSERT().
696 If Length > 0 and Destination is not aligned on a 16-bit boundary, then ASSERT().
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/freebsd/sys/dev/liquidio/base/
H A Dcn23xx_pf_regs.h60 /* 2 scatch registers (64-bit) */
66 /* 1 registers (64-bit) - SLI_CTL_STATUS */
70 * SLI Packet Input Jabber Register (64 bit register)
96 * 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
101 /*1 register (64-bit) to determine whether IOQs are in reset. */
118 /* Starting bit of the TRS field in LIO_CN23XX_SLI_PKT_MAC_RINFO64 register */
123 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
126 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
129 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
132 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64GenRegisterBankInfo.def16 // 0: FPR 16-bit value.
18 // 1: FPR 32-bit value.
20 // 2: FPR 64-bit value.
21 {0, 64, AArch64::FPRRegBank},
22 // 3: FPR 128-bit value.
24 // 4: FPR 256-bit value.
26 // 5: FPR 512-bit value.
28 // 6: GPR 32-bit value.
30 // 7: GPR 64-bit value.
31 {0, 64, AArch64::GPRRegBank},
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
15 def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide
17 def WriteIDiv32 : SchedWrite; // 32-bit divide on RV64I
18 def WriteIRem : SchedWrite; // 32-bit or 64-bit remainder
19 def WriteIRem32 : SchedWrite; // 32-bit remainder on RV64I
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/ppc/
H A Dfloattitf.c9 // This file implements converting a signed 128 bit integer to a 128bit IBM /
16 // Conversions from signed and unsigned 64-bit int to long double.
20 // Convert a signed 128-bit integer to long double.
21 // This uses the following property: Let hi and lo be 64-bits each,
23 // argument interpreted as a signed or unsigned k-bit integer. Then,
25 // signed_val_128(hi,lo) = signed_val_64(hi) * 2^64 + unsigned_val_64(lo)
26 // = (long double)hi * 2^64 + (long double)lo,
29 // unsigned 64-bit integer to long double conversions, respectively.
31 // Split the int128 argument into 64-bit high and low int64 parts. in __floattitf()
32 int64_t ArgHiPart = (int64_t)(arg >> 64); in __floattitf()
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/freebsd/sys/contrib/dev/acpica/components/tables/
H A Dtbfadt.c330 * Bit width field in the GAS is only one byte long, 255 max. in AcpiTbInitGenericAddress()
344 "%s - 32-bit FADT register is too long (%u bytes, %u bits) " in AcpiTbInitGenericAddress()
353 * The 64-bit Address field is non-aligned in the byte packed in AcpiTbInitGenericAddress()
372 * Address32 - 32-bit address of the register
373 * Address64 - 64-bit address of the register
375 * RETURN: The resolved 64-bit address
377 * DESCRIPTION: Select between 32-bit and 64-bit versions of addresses within
383 * the 32-bit and 64-bit address fields (FIRMWARE_CTRL/X_FIRMWARE_CTRL and
388 * By default, as per the ACPICA specification, a valid 64-bit address is
389 * used regardless of the value of the 32-bit address. However, this
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/freebsd/contrib/xz/src/liblzma/check/
H A Dcrc_clmul_consts_gen.c10 /// This is for CRCs that use reversed bit order (bit reflection).
13 /// Barrett reduction to handle the 65th bit; the smaller ones don't.
43 // Align the x^64 term with the x^128 (the implied high bits of the in calc_cldiv()
46 // zero because the highest bit of the quotient is an implied bit 1 in calc_cldiv()
50 // Then process the remaining 64 terms. Note that r has no implied in calc_cldiv()
51 // high bit, only q and p do. (And remember that a high bit in the in calc_cldiv()
52 // polynomial is stored at a low bit in the variable due to the in calc_cldiv()
53 // reversed bit order.) in calc_cldiv()
54 for (unsigned i = 0; i < 64; ++i) { in calc_cldiv()
65 /// x^(bits + n - 1) % p, where n=64 (for CRC64)
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/freebsd/contrib/libcxxrt/
H A Dguard.cc37 * Statics that require initialisation are protected by a 64-bit value. Any
38 * platform that can do 32-bit atomic test and set operations can use this
66 * The Itanium C++ ABI defines guard words that are 64-bit (32-bit on AArch32)
67 * values with one bit defined to indicate that the guarded variable is and
68 * another bit to indicate that it's currently locked (initialisation in
69 * progress). The bit to use depends on the byte order of the target.
71 * On many 32-bit platforms, 64-bit atomics are unavailable (or slow) and so we
72 * treat the two halves of the 64-bit word as independent values and establish
105 * guard. The word size is defined by the type of `GuardWord`. The bit
106 * used to indicate the locked state is `1<<LockedBit`, the bit used to
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/freebsd/contrib/llvm-project/libcxx/src/include/ryu/
H A Dd2s_intrinsics.h60 // modulo 64. in __ryu_shiftright128()
62 // of Ryu, the shift value is always < 64. in __ryu_shiftright128()
66 _LIBCPP_ASSERT_INTERNAL(__dist < 64, ""); in __ryu_shiftright128()
78 *__productHi = __temp >> 64;
84 // of Ryu, the shift value is always < 64.
88 _LIBCPP_ASSERT_INTERNAL(__dist < 64, "");
89 auto __temp = __lo | ((unsigned __int128)__hi << 64);
90 // For x64 128-bit shfits using the `shrd` instruction and two 64-bit
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/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DMathExtras.h16 #include "llvm/ADT/bit.h"
84 assert(N <= Bits && "Invalid bit index"); in maskTrailingOnes()
108 /// Macro compressed bit reversal table for 256 bits.
112 #define R2(n) n, n + 2 * 64, n + 1 * 64, n + 3 * 64
153 /// Return the high 32 bits of a 64 bit value.
158 /// Return the low 32 bits of a 64 bit value.
163 /// Make a 64-bit integer from a high / low pair of 32-bit integers.
168 /// Checks if an integer fits into the given bit width.
178 if constexpr (N < 64) in isInt()
184 /// Checks if a signed integer is an N bit number shifted left by S.
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