Lines Matching +full:64 +full:bit

15 stored internally as ten 32-bit capability vectors and for simplicity
16 represented logically below as five 64-bit vectors. This logical
22 environment variable capability bit modifications are applied. After toolkit
39 =item bit #0+4 denoting presence of Time-Stamp Counter;
41 =item bit #0+19 denoting availability of CLFLUSH instruction;
43 =item bit #0+20, reserved by Intel, is used to choose among RC4 code paths;
45 =item bit #0+23 denoting MMX support;
47 =item bit #0+24, FXSR bit, denoting availability of XMM registers;
49 =item bit #0+25 denoting SSE support;
51 =item bit #0+26 denoting SSE2 support;
53 =item bit #0+28 denoting Hyperthreading, which is used to distinguish
56 =item bit #0+30, reserved by Intel, denotes specifically Intel CPUs;
58 =item bit #0+33 denoting availability of PCLMULQDQ instruction;
60 =item bit #0+41 denoting SSSE3, Supplemental SSE3, support;
62 =item bit #0+43 denoting AMD XOP support (forced to zero on non-AMD CPUs);
64 =item bit #0+54 denoting availability of MOVBE instruction;
66 =item bit #0+57 denoting AES-NI instruction set extension;
68 =item bit #0+58, XSAVE bit, lack of which in combination with MOVBE is used
71 =item bit #0+59, OSXSAVE bit, denoting availability of YMM registers;
73 =item bit #0+60 denoting AVX extension;
75 =item bit #0+62 denoting availability of RDRAND instruction;
87 =item bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;
89 =item bit #64+5 denoting availability of AVX2 instructions;
91 =item bit #64+8 denoting availability of BMI2 instructions, e.g. MULX
94 =item bit #64+16 denoting availability of AVX512F extension;
96 =item bit #64+17 denoting availability of AVX512DQ extension;
98 =item bit #64+18 denoting availability of RDSEED instruction;
100 =item bit #64+19 denoting availability of ADCX and ADOX instructions;
102 =item bit #64+21 denoting availability of AVX512IFMA extension;
104 =item bit #64+29 denoting availability of SHA extension;
106 =item bit #64+30 denoting availability of AVX512BW extension;
108 =item bit #64+31 denoting availability of AVX512VL extension;
110 =item bit #64+41 denoting availability of VAES extension;
112 =item bit #64+42 denoting availability of VPCLMULQDQ extension;
124 =item bit #128+15 denoting availability of Hybrid CPU;
126 =item bit #128+29 denoting support for IA32_ARCH_CAPABILITIES MSR;
128 =item bit #128+32 denoting availability of SHA512 extension;
130 =item bit #128+33 denoting availability of SM3 extension;
132 =item bit #128+34 denoting availability of SM4 extension;
134 =item bit #128+55 denoting availability of AVX-IFMA extension;
146 =item bit #192+19 denoting availability of AVX10 Converged Vector ISA extension;
148 =item bit #192+21 denoting availability of APX_F extension;
162 =item bit #256+48 denoting AVX10 XMM support;
164 =item bit #256+49 denoting AVX10 YMM support;
166 =item bit #256+50 denoting AVX10 ZMM support;
174 The variable consists of a series of 64-bit numbers representing each
198 The 'B<~>' character is used to specify a bit mask of the extensions to be disabled for
205 The following will disable AESNI (LV0 bit 57) and VAES (LV1 bit 41)
214 of this is the somewhat less intuitive clearing of LV0 bit #28, or ~0x10000000