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/linux/include/linux/
H A Dmath64.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #if BITS_PER_LONG == 64
16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
[all …]
H A Dexportfs.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 * 32bit inode number, 32 bit generation number.
39 * 32bit inode number, 32 bit generation number,
40 * 32 bit parent directory inode number.
45 * 64 bit object ID, 64 bit root object ID,
46 * 32 bit generation number.
51 * 64 bit object ID, 64 bit root object ID,
52 * 32 bit generation number,
53 * 64 bit parent object ID, 32 bit parent generation.
58 * 64 bit object ID, 64 bit root object ID,
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
[all …]
/linux/arch/x86/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 tristate "Ciphers: AES, modes: ECB, CBC, CTS, CTR, XCTR, XTS, GCM (AES-NI/VAES)"
15 Length-preserving ciphers: AES with ECB, CBC, CTS, CTR, XCTR, XTS
17 Architecture: x86 (32-bit and 64-bit) using:
18 - AES-NI (AES new instructions)
19 - VAES (Vector AES)
21 Some algorithm implementations are supported only in 64-bit builds,
26 depends on 64BIT
32 Length-preserving ciphers: Blowfish with ECB and CBC modes
38 depends on 64BIT
[all …]
/linux/drivers/gpio/
H A Dgpio-xilinx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2008 - 2013 Xilinx, Inc.
31 #define XGPIO_GIER_IE BIT(31)
45 * struct xgpio_instance - Stores information about GPIO device
62 DECLARE_BITMAP(map, 64);
63 DECLARE_BITMAP(state, 64);
64 DECLARE_BITMAP(last_irq_read, 64);
65 DECLARE_BITMAP(dir, 64);
68 DECLARE_BITMAP(enable, 64);
69 DECLARE_BITMAP(rising_edge, 64);
[all …]
/linux/arch/parisc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T if !64BIT
20 select ARCH_SPLIT_ARG64 if !64BIT
40 select GENERIC_ATOMIC64 if !64BIT
84 select HAVE_DYNAMIC_FTRACE if $(cc-option,-fpatchable-function-entry=1,1)
90 select HAVE_FUNCTION_DESCRIPTORS if 64BIT
94 The PA-RISC microprocessor is designed by Hewlett-Packard and used
96 and later HP3000 series). The PA-RISC Linux project home page is
124 select GENERIC_BUG_RELATIVE_POINTERS if 64BIT
143 default 18 if 64BIT
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn23xx_pf_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
83 /* SLI Packet Input Jabber Register (64 bit register)
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
125 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
141 /* Starting bit of the TRS field in CN23XX_SLI_PKT_MAC_RINFO64 register */
143 /* Starting bit of SRN field in CN23XX_SLI_PKT_MAC_RINFO64 register */
[all …]
H A Dcn23xx_vf_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
47 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
52 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
55 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
58 /* 64 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
61 /* 64 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
64 /* 64 registers (64-bit) - ES, RO, NS, Arbitration for Input Queue Data &
69 /*------- Request Queue Macros ---------*/
85 /*------------------ Masks ----------------*/
[all …]
H A Dcn66xx_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
106 /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
109 /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */
112 /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
[all …]
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Copyright (C) 2007-2016 Broadcom Corporation.
9 * Copyright (C) 2016-2017 Broadcom Limited.
21 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
22 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
27 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
78 /* 0x04 --> 0x2c unused */
115 /* 0x30 --> 0x64 unused */
117 /* 0x66 --> 0x68 unused */
284 /* 0x94 --> 0x98 unused */
[all …]
/linux/drivers/acpi/acpica/
H A Dtbfadt.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: tbfadt - FADT table utilities
6 * Copyright (C) 2000 - 2025, Intel Corp.
143 * PARAMETERS: generic_address - GAS struct to be initialized
144 * space_id - ACPI Space ID for this register
145 * byte_width - Width of this register
146 * address - Address of the register
147 * register_name - ASCII name of the ACPI register
166 * Bit width field in the GAS is only one byte long, 255 max. in acpi_tb_init_generic_address()
178 "%s - 32-bit FADT register is too long (%u bytes, %u bits) " in acpi_tb_init_generic_address()
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H A Dtbutils.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: tbutils - ACPI Table utilities
6 * Copyright (C) 2000 - 2025, Intel Corp.
78 if (acpi_gbl_original_dsdt_header.length != acpi_gbl_DSDT->length || in acpi_tb_check_dsdt_header()
79 acpi_gbl_original_dsdt_header.checksum != acpi_gbl_DSDT->checksum) { in acpi_tb_check_dsdt_header()
81 "The DSDT has been corrupted or replaced - " in acpi_tb_check_dsdt_header()
88 "Please send DMI info to linux-acpi@vger.kernel.org\n" in acpi_tb_check_dsdt_header()
93 acpi_gbl_original_dsdt_header.length = acpi_gbl_DSDT->length; in acpi_tb_check_dsdt_header()
95 acpi_gbl_DSDT->checksum; in acpi_tb_check_dsdt_header()
103 * PARAMETERS: table_index - Index of installed table to copy
[all …]
/linux/lib/math/
H A Ddiv64.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on former do_div() implementation from asm-parisc/div64.h:
6 * Copyright (C) 1999 Hewlett-Packard Co
7 * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
16 * for some CPUs. __div64_32() can be overridden by linking arch-specific
28 /* Not needed on 64bit architectures */
39 /* Reduce the thing a bit first */ in __div64_32()
44 rem -= (uint64_t) (high*base) << 32; in __div64_32()
[all …]
/linux/drivers/net/can/flexcan/
H A Dflexcan.h1 /* SPDX-License-Identifier: GPL-2.0
2 * flexcan.c - FLEXCAN CAN controller driver
4 * Copyright (c) 2005-2006 Varma Electronics Oy
6 * Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
10 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
17 #include <linux/can/rx-offload.h>
22 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode MB
25 * MX25 FlexCAN2 03.00.00.00 no no no no no no 64
26 * MX28 FlexCAN2 03.00.04.00 yes yes no no no no 64
27 * MX35 FlexCAN2 03.00.00.00 no no no no no no 64
[all …]
/linux/include/xen/interface/
H A Dcallback.h1 /* SPDX-License-Identifier: MIT */
19 * @extra_args == Operation-specific extra arguments (NULL if none).
28 /* x86/64 hypervisor: Syscall by 64-bit guest app ('64-on-64-on-64'). */
42 * - 32-bit hypervisor: with the supervisor_mode_kernel feature enabled
43 * - 64-bit hypervisor: 32-bit guest applications on Intel CPUs
44 * ('32-on-32-on-64', '32-on-64-on-64')
45 * [nb. also 64-bit guest applications on Intel CPUs
46 * ('64-on-64-on-64'), but syscall is preferred]
51 * x86/64 hypervisor: Syscall by 32-bit guest app on AMD CPUs
52 * ('32-on-32-on-64', '32-on-64-on-64')
[all …]
/linux/lib/crc/x86/
H A Dcrc-pclmul-template.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 // Template to generate [V]PCLMULQDQ-based CRC functions for x86
13 .set OFFSETOF_BSWAP_MASK, -5*16 // msb-first CRCs only
14 .set OFFSETOF_FOLD_ACROSS_2048_BITS_CONSTS, -4*16 // must precede next
15 .set OFFSETOF_FOLD_ACROSS_1024_BITS_CONSTS, -3*16 // must precede next
16 .set OFFSETOF_FOLD_ACROSS_512_BITS_CONSTS, -2*16 // must precede next
17 .set OFFSETOF_FOLD_ACROSS_256_BITS_CONSTS, -1*16 // must precede next
23 // corresponding non-VEX instruction plus any needed moves. The supported
26 // - Two-arg [src, dst], where the non-VEX format is the same.
27 // - Three-arg [src1, src2, dst] where the non-VEX format is
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
57 * bit will be set. Otherwise the value of the register before
67 * bit will be set. Otherwise the value of the register before
77 * bit will be set. Otherwise the value of the register before
87 * bit will be set. Otherwise the value of the register before
97 * the error bit will be set. Otherwise the value of the
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
[all …]
/linux/arch/mips/kernel/
H A Dunaligned.c18 * only the performance is affected. Much worse is that such code is non-
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
92 #include <asm/unaligned-emul.h>
97 #include "access-helper.h"
121 orig31 = regs->regs[31]; in emulate_load_store_insn()
133 * can assume therefore that the code is MIPS-aware and in emulate_load_store_insn()
177 regs->regs[insn.mxu_lx_format.rd] = value; in emulate_load_store_insn()
186 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
195 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
[all …]
/linux/arch/x86/um/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
15 config 64BIT config
16 bool "64-bit kernel" if "$(SUBARCH)" = "x86"
20 def_bool !64BIT
29 def_bool 64BIT
33 def_bool !64BIT
36 def_bool !64BIT
/linux/lib/tests/
H A Dffs_kunit.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * KUnit tests for ffs()-family functions
13 int expected_ffs; /* ffs() result (1-based) */
14 int expected_fls; /* fls() result (1-based) */
20 int expected_fls64; /* fls64() result (1-based) */
21 unsigned int expected_ffs64_0based; /* __ffs64() result (0-based) */
26 * Basic edge cases - core functionality validation
29 /* Zero case - special handling */
32 /* Single bit patterns - powers of 2 */
33 {0x00000001, 1, 1, "bit 0 set"},
[all …]
/linux/Documentation/bpf/standardization/
H A Dinstruction-set.rst27 BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_
28 `<https://www.rfc-editor.org/info/rfc8174>`_
38 -----
40 a type's signedness (`S`) and bit width (`N`), respectively.
51 .. table:: Meaning of bit-width notation
54 N Bit width
59 64 64 bits
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
64 numbers and `s16` is a type whose valid values are all the 16-bit signed
68 ---------
[all …]
/linux/lib/crc/s390/
H A Dcrc32be-vx.c1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of CRC-32 checksums.
8 * This CRC-32 implementation algorithm processes the most-significant
9 * bit first (BE).
17 #include "crc32-vx.h"
19 /* Vector register range containing CRC-32 constants */
28 * The CRC-32 constant block contains reduction constants to fold and
31 * For the CRC-32 variants, the constants are precomputed according to
34 * R1 = x4*128+64 mod P(x)
[all …]
/linux/Documentation/bpf/
H A Dclassic_vs_extended.rst12 - Number of registers increase from 2 to 10:
15 new layout extends this to be 10 internal registers and a read-only frame
16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
17 the number of args from eBPF program to in-kernel function is restricted
18 to 5 and one register is used to accept return value from an in-kernel
20 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
33 call predefined in-kernel functions, though.
[all …]
/linux/arch/x86/math-emu/
H A Dwm_shrx.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 /*---------------------------------------------------------------------------+
6 | 64 bit right shift functions |
10 | Australia. E-mail billm@jacobi.maths.monash.edu.au |
17 +---------------------------------------------------------------------------*/
22 /*---------------------------------------------------------------------------+
27 | Shifts the 64 bit quantity pointed to by the first arg (arg1) |
29 | Forms a 96 bit quantity from the 64 bit arg and eax: |
30 | [ 64 bit arg ][ eax ] |
31 | shift right ---------> |
[all …]
/linux/arch/mips/net/
H A Dbpf_jit_comp64.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Just-In-Time compiler for eBPF bytecode on MIPS.
4 * Implementation of JIT functions for 64-bit CPUs.
18 #include <asm/cpu-features.h>
19 #include <asm/isa-rev.h>
24 /* MIPS t0-t3 are not available in the n64 ABI */
30 /* Stack is 16-byte aligned in n64 ABI */
33 /* Extra 64-bit eBPF registers used by JIT */
40 /* Callee-saved CPU registers that the JIT must preserve */
42 (BIT(MIPS_R_S0) | \
[all …]

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