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/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
28 mode "640x480-60"
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
[all …]
H A Dmatroxfb.rst291 maxclk:X maximum dotclock. X can be specified in MHz, kHz or Hz. Default is
296 70 for modes derived from `vesa` with yres <= 400, 60Hz for
324 - 83 MHz on G200
325 - 66 MHz on Millennium I
326 - 60 MHz on Millennium II
332 - my Millennium G200 oscillator has frequency range from 35 MHz to 380 MHz
333 (and it works with 8bpp on about 320 MHz dotclocks (and changed mclk)).
334 But Matrox says on product sheet that VCO limit is 50-250 MHz, so I believe
361 It is time to redraw whole screen 1000 times in 1024x768, 60Hz. It is
366 faster, it is kernel-space only time on P-II/350 MHz, Millennium I in 33 MHz
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/linux/drivers/video/fbdev/
H A Dvalkyriefb.h79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
126 /* Register values for 1024x768, 60Hz mode (14) */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
151 /* Register values for 800x600, 60Hz mode (10) */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
[all …]
/linux/drivers/phy/nuvoton/
H A Dphy-ma35d1-usb2.c22 #define PHY0DEVCKSTB BIT(10) /* PHY 60 MHz UTMI clock stable bit */
46 * make sure USB PHY 60 MHz UTMI Interface Clock ready in ma35_usb_phy_power_on()
56 * wait until USB PHY0 60 MHz UTMI Interface Clock ready in ma35_usb_phy_power_on()
64 /* make sure USB PHY 60 MHz UTMI Interface Clock ready */ in ma35_usb_phy_power_on()
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dphy_shim.h45 #define FRA_ERR_20MHZ 60
80 /* Index for first 20MHz OFDM SISO rate */
82 /* Index for first 20MHz OFDM CDD rate */
84 /* Index for first 40MHz OFDM SISO rate */
86 /* Index for first 40MHz OFDM CDD rate */
87 #define WL_TX_POWER_OFDM40_CDD_FIRST 60
89 /* Index for first 20MHz MCS SISO rate */
91 /* Index for first 20MHz MCS CDD rate */
93 /* Index for first 20MHz MCS STBC rate */
95 /* Index for first 20MHz MCS SDM rate */
[all …]
/linux/arch/powerpc/boot/
H A Dutil.S22 * timebase in nanoseconds. This used to be hardcoded to be 60ns
23 * (period of 66MHz/4). Now a variable is used that is initialized to
24 * 60 for backward compatibility, but it can be overridden as necessary
32 .long 60
43 * timebase_period_ns defaults to 60 (16.6MHz) */
/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-enumstd.rst136 ``V4L2_STD_PAL_60`` is a hybrid standard with 525 lines, 60 Hz refresh
137 rate, and PAL color modulation with a 4.43 MHz color subcarrier. Some
139 a 50/60 Hz agnostic PAL TV.
147 ``V4L2_STD_NTSC_443`` is a hybrid standard with 525 lines, 60 Hz refresh
148 rate, and NTSC color modulation with a 4.43 MHz color subcarrier.
268 * - Nominal radio-frequency channel bandwidth (MHz)
280 * - Sound carrier relative to vision carrier (MHz)
331 New Zealand uses a sound carrier displaced 5.4996 ± 0.0005 MHz from
337 is being introduced. The second carrier is 5.85 MHz above the vision
343 second sound carrier is 6.552 MHz above the vision carrier and is
[all …]
/linux/drivers/mmc/host/
H A Dsdhci-of-arasan.c83 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
86 #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
206 * met at 25MHz for Default Speed mode, those controllers work at
207 * 19MHz instead
407 * requirements met at 25MHz for Default Speed mode, in sdhci_arasan_set_clock()
408 * those controllers work at 19MHz instead. in sdhci_arasan_set_clock()
789 /* For 50MHz clock, 30 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
793 /* For 100MHz cloc in sdhci_zynqmp_sdcardclk_set_phase()
1229 u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); sdhci_arasan_update_baseclkfreq() local
1782 u32 mhz, node_id = !strcmp(clk_name, "clk_out_sd0") ? NODE_SD_0 : NODE_SD_1; sdhci_zynqmp_set_dynamic_config() local
[all...]
/linux/Documentation/admin-guide/media/
H A Dvivid.rst334 framerate of 59.94 Hz is really different from 60 Hz. If the framerate
344 supports frames per second settings of 10, 15, 25, 30, 50 and 60 fps. Which ones
368 is the newest in time. For 60 Hz standards that is reversed: the bottom field
372 contain the top field for 50 Hz standards and the bottom field for 60 Hz
387 The TV 'tuner' supports a frequency range of 44-958 MHz. Channels are available
388 every 6 MHz, starting from 49.25 MHz. For each channel the generated image
389 will be in color for the +/- 0.25 MHz around it, and in grayscale for
390 +/- 1 MHz around the channel. Beyond that it is just noise. The VIDIOC_G_TUNER
391 ioctl will return 100% signal strength for +/- 0.25 MHz and 50% for +/- 1 MHz.
395 The audio subchannels that are returned are MONO for the +/- 1 MHz range around
[all …]
/linux/drivers/media/dvb-frontends/
H A Dcx24110.c49 {0x06,0xa5}, /* @ PLL 60MHz */
50 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
244 /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz, in cx24110_set_symbolrate()
248 if(srate<90999000UL/4) { /* sample rate 45MHz*/ in cx24110_set_symbolrate()
252 } else if(srate<60666000UL/2) { /* sample rate 60MHz */ in cx24110_set_symbolrate()
256 } else if(srate<80888000UL/2) { /* sample rate 80MHz */ in cx24110_set_symbolrate()
260 } else { /* sample rate 90MHz */ in cx24110_set_symbolrate()
549 /* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz. in cx24110_get_frontend()
619 .frequency_min_hz = 950 * MHz,
620 .frequency_max_hz = 2150 * MHz,
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-icore-rqs.dtsi182 txd0-skew-ps = <60>;
183 txd1-skew-ps = <60>;
184 txd2-skew-ps = <60>;
400 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
411 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
437 pinctrl_usdhc4_100mhz: usdhc4-100mhz-grp {
452 pinctrl_usdhc4_200mhz: usdhc4-200mhz-grp {
/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
16 {cpu_to_le16(160), {50, 58, 60, 62, 64, 52, 54, 56},
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dmaxim,max8952.yaml62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
91 pmic@60 {
/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c17 * NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
26 * ref_freq = 28.636360 MHz
28 * ref_freq = 28.636363 MHz
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
47 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
53 * 196.6 MHz pre-postdivide in cx25840_set_audclk_freq()
54 * FIXME < 200 MHz is out of specified valid range in cx25840_set_audclk_freq()
84 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
85 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
91 * 271 MHz pre-postdivide in cx25840_set_audclk_freq()
[all …]
/linux/arch/sh/
H A DKconfig294 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
300 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
306 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
307 if you have a 100 Mhz SH-3 HD6417708R CPU.
313 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
354 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
375 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574-rdp-common.dtsi61 debounce-interval = <60>;
122 * During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
127 * corner parts to operate at 800MHz
280 * (48 MHZ or 96 MHZ used for different RDP type board). This setting
282 * clock output from WiFi to the CMN PLL is 48 MHZ.
290 * The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
291 * from WiFi output clock 48 MHZ divided by 2.
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
124 Defines the auto PD disable frequency in MHz.
128 minimum: 1000000 # In case anyone thought this was MHz.
176 minimum: 1000000 # In case anyone thought this was MHz.
223 minimum: 1000000 # In case anyone thought this was MHz.
235 default: 60
283 default: 60
/linux/drivers/media/usb/gspca/
H A Dmars.c264 * 0x30 for 24mhz , 0x28 for 12mhz */ in sd_start()
269 /* data[9]= 0x56; * reg 8, 24MHz, 2:1 scale down */ in sd_start()
271 data[9] = 0x52; /* reg 8, 24MHz, no scale down */ in sd_start()
284 /* data[1] = 200; * reg 60, pc-cam frame size in sd_start()
287 data[1] = 50; /* 50 reg 60, pc-cam frame size in sd_start()
296 /* h (60): xxxx x100 in sd_start()
/linux/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c33 const u32 mhz = 1000000; in dphy_calc_pll_param() local
66 tmp = pll->fvco * factor * mhz; in dphy_calc_pll_param()
68 tmp = tmp - pll->nint * factor * mhz; in dphy_calc_pll_param()
265 range[L] = 60 * scale; in dphy_timing_config()
268 range[L] = max(8 * t_ui, 60 * scale + 4 * t_ui); in dphy_timing_config()
280 range[L] = 60 * scale + 52 * t_ui; in dphy_timing_config()
/linux/Documentation/devicetree/bindings/input/
H A Diqs269a.yaml180 0: 16 MHz (4 MHz)
181 1: 8 MHz (2 MHz)
182 2: 4 MHz (1 MHz)
183 3: 2 MHz (500 kHz)
221 approximately 60-ms pulse to be asserted on the GPIO4 pin.
336 Decreases the internal measurement capacitance from 60 pF to 15 pF.
389 0: 4 MHz (1 MHz)
390 1: 2 MHz (500 kHz)
391 2: 1 MHz (250 kHz)
/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c41 .m = {.min = 60, .max = 160},
53 .m = {.min = 60, .max = 160},
58 /* The single-channel range is 25-112Mhz, and dual-channel
59 * is 80-224Mhz. Prefer single channel as much as possible.
80 .m = {.min = 60, .max = 160},
104 .m = {.min = 60, .max = 164},
629 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
632 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
639 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise in cdv_intel_crtc_mode_set()
640 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose in cdv_intel_crtc_mode_set()
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h846 * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
847 * FS and LS modes, the PHY can usually operate on a 48-MHz
849 * * 1'b0: 480-MHz Internal PLL clock
850 * * 1'b1: 48-MHz External Clock
851 * In 480 MHz mode, the UTMI interface operates at either 60 or
852 * 30-MHz, depending upon whether 8- or 16-bit data width is
853 * selected. In 48-MHz mode, the UTMI interface operates at 48
854 * MHz in FS mode and at either 48 or 6 MHz in LS mode
891 * * One 30-MHz PHY clock = 16 bit times
892 * * One 60-MHz PHY clock = 8 bit times
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dqcom,dwc3.yaml97 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
98 60MHz for HS operation.
103 mode. Its frequency should be 19.2MHz.
205 - description: Master/Core clock, has to be >= 125 MHz
206 for SS operation and >= 60MHz for HS operation.
H A Dqcom,snps-dwc3.yaml91 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
92 60MHz for HS operation.
97 mode. Its frequency should be 19.2MHz.
195 - description: Master/Core clock, has to be >= 125 MHz
196 for SS operation and >= 60MHz for HS operation.

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