Lines Matching +full:60 +full:mhz
40 .m = {.min = 60, .max = 160},
52 .m = {.min = 60, .max = 160},
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
79 .m = {.min = 60, .max = 160},
103 .m = {.min = 60, .max = 164},
628 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
631 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
638 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise in cdv_intel_crtc_mode_set()
639 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose in cdv_intel_crtc_mode_set()
640 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. in cdv_intel_crtc_mode_set()
650 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); in cdv_intel_crtc_mode_set()
884 /* XXX: might not be 66MHz */ in cdv_intel_crtc_clock_get()