Home
last modified time | relevance | path

Searched +full:60 +full:mhz (Results 1 – 25 of 237) sorted by relevance

12345678910

/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/freebsd/sys/dev/usb/video/
H A Dudl.h138 static const uint8_t udl_reg_vals_640x480_60[UDL_MODE_SIZE] = { /* 25.17 Mhz 59.9 Hz
144 static const uint8_t udl_reg_vals_640x480_67[UDL_MODE_SIZE] = { /* 30.25 MHz 66.6 Hz MAC
150 static const uint8_t udl_reg_vals_640x480_72[UDL_MODE_SIZE] = { /* 31.50 Mhz 72.8 Hz
156 static const uint8_t udl_reg_vals_640x480_75[UDL_MODE_SIZE] = { /* 31.50 Mhz 75.7 Hz
162 static const uint8_t udl_reg_vals_800x480_61[UDL_MODE_SIZE] = { /* 33.00 MHz 61.9 Hz */
167 static const uint8_t udl_reg_vals_800x600_56[UDL_MODE_SIZE] = { /* 36.00 MHz 56.2 Hz
173 static const uint8_t udl_reg_vals_800x600_60[UDL_MODE_SIZE] = { /* 40.00 MHz 60.3 Hz
179 static const uint8_t udl_reg_vals_800x600_72[UDL_MODE_SIZE] = { /* 50.00 MHz 72.1 Hz
185 static const uint8_t udl_reg_vals_800x600_74[UDL_MODE_SIZE] = { /* 50.00 MHz 74.4 Hz */
190 static const uint8_t udl_reg_vals_800x600_75[UDL_MODE_SIZE] = { /* 49.50 MHz 75.0 Hz
[all …]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c1375 * @freq: Frequency (MHz) to convert
1701 case 32: /* channels 1..7; 40 MHz */ in ieee80211_chan_to_freq_us()
1702 case 33: /* channels 5..11; 40 MHz */ in ieee80211_chan_to_freq_us()
1707 case 2: /* channels 52,56,60,64; dfs */ in ieee80211_chan_to_freq_us()
1708 case 22: /* channels 36,44; 40 MHz */ in ieee80211_chan_to_freq_us()
1709 case 23: /* channels 52,60; 40 MHz */ in ieee80211_chan_to_freq_us()
1710 case 27: /* channels 40,48; 40 MHz */ in ieee80211_chan_to_freq_us()
1711 case 28: /* channels 56,64; 40 MHz */ in ieee80211_chan_to_freq_us()
1716 case 24: /* channels 100-140; 40 MHz */ in ieee80211_chan_to_freq_us()
1721 case 25: /* channels 149,157; 40 MHz */ in ieee80211_chan_to_freq_us()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt64 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
70 MHz (Mega Hz). When DDR frequency is less than
75 the ODT disable frequency in MHz (Mega Hz).
101 then ODT disable frequency in MHz (Mega Hz).
128 MHz (Mega Hz). When the DDR frequency is less then
134 value is 60.
157 the PHY side ODT strength. Default value is 60.
205 rockchip,lpddr4_drv = <60>;
211 rockchip,phy_lpddr4_odt = <60>;
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_dfs.c29 /* 20MHz */
34 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
38 /* 40MHz */
43 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
47 /* 80MHz */
52 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
59 /* 20MHz */
66 RADAR_SPEC(2, 60, 15, 63, 640, 2080, 32, 19600, 40200, 32, 0,
68 /* 40MHz */
75 RADAR_SPEC(2, 60, 15, 63, 640, 2080, 32, 19600, 40200, 32, 0,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dmax8952.txt15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
33 vdd_arm_reg: pmic@60 {
H A Dmaxim,max8952.yaml62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
91 pmic@60 {
/freebsd/sys/net80211/
H A Dieee80211_dfs.c56 static int ieee80211_nol_timeout = 30*60; /* 30 minutes */
61 static int ieee80211_cac_timeout = 60; /* 60 seconds */
148 "CAC timer on channel %u (%u MHz) stopped due to radar\n", in cac_timeout()
157 "CAC timer on channel %u (%u MHz) expired; " in cac_timeout()
190 if_printf(vap->iv_ifp, "start %d second CAC timer on channel %u (%u MHz)\n", in ieee80211_dfs_cac_start()
209 if_printf(vap->iv_ifp, "stop CAC timer on channel %u (%u MHz)\n", in ieee80211_dfs_cac_stop()
253 "(%u MHz) cleared after timeout\n", in dfs_timeout()
275 ic_printf(ic, "radar detected on channel %u (%u MHz)\n", in announce_radar()
278 ic_printf(ic, "radar detected on channel %u (%u MHz), " in announce_radar()
279 "moving to channel %u (%u MHz)\n", in announce_radar()
H A Dieee80211_regdomain.h62 CTRY_BERMUDA = 60,
258 SKU_SR9 = 0x0298, /* Ubiquiti SR9 (900MHz/GSM) */
259 SKU_XR9 = 0x0299, /* Ubiquiti XR9 (900MHz/GSM) */
260 SKU_GZ901 = 0x029a, /* Zcomax GZ-901 (900MHz/GSM) */
261 SKU_XC900M = 0x029b, /* Xagyl XC900M (900MHz/GSM) */
266 * offset channel spacing (905MHz-
267 * 925MHz) versus the XR9 (907MHz-
268 * 922MHz), giving an extra channel.
/freebsd/sys/contrib/dev/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
16 {cpu_to_le16(160), {50, 58, 60, 62, 64, 52, 54, 56},
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
[all...]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-icore-rqs.dtsi182 txd0-skew-ps = <60>;
183 txd1-skew-ps = <60>;
184 txd2-skew-ps = <60>;
400 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
411 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
437 pinctrl_usdhc4_100mhz: usdhc4-100mhz-grp {
452 pinctrl_usdhc4_200mhz: usdhc4-200mhz-grp {
/freebsd/sys/contrib/dev/iwlwifi/cfg/
H A Dax210.c105 .d3_debug_data_length = 60 * 1024, \
201 const char iwl_ax211_name[] = "Intel(R) Wi-Fi 6E AX211 160MHz";
202 const char iwl_ax221_name[] = "Intel(R) Wi-Fi 6E AX221 160MHz";
203 const char iwl_ax231_name[] = "Intel(R) Wi-Fi 6E AX231 160MHz";
204 const char iwl_ax411_name[] = "Intel(R) Wi-Fi 6E AX411 160MHz";
207 "Killer(R) Wi-Fi 6E AX1675w 160MHz Wireless Network Adapter (210D2W)";
209 "Killer(R) Wi-Fi 6E AX1675x 160MHz Wireless Network Adapter (210NGW)";
211 "Killer(R) Wi-Fi 6E AX1675s 160MHz Wireless Network Adapter (211NGW)";
213 "Killer(R) Wi-Fi 6E AX1675i 160MHz Wireless Network Adapter (211NGW)";
215 "Killer(R) Wi-Fi 6E AX1690s 160MHz Wireles
[all...]
H A D22000.c93 .d3_debug_data_length = 60 * 1024, \
205 const char iwl_ax200_name[] = "Intel(R) Wi-Fi 6 AX200 160MHz";
206 const char iwl_ax201_name[] = "Intel(R) Wi-Fi 6 AX201 160MHz";
208 const char iwl_ax204_name[] = "Intel(R) Wi-Fi 6 AX204 160MHz";
211 "Killer(R) Wi-Fi 6 AX1650w 160MHz Wireless Network Adapter (200D2W)";
213 "Killer(R) Wi-Fi 6 AX1650x 160MHz Wireless Network Adapter (200NGW)";
215 "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)";
217 "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)";
245 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
283 .name = "Intel(R) Wi-Fi 6 AX201 160MHz",
[all...]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Ddwc3-xilinx.txt8 "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
9 operation and >= 60MHz for HS operation
H A Dqcom,dwc3.yaml81 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
82 60MHz for HS operation.
87 mode. Its frequency should be 19.2MHz.
189 - description: Master/Core clock, has to be >= 125 MHz
190 for SS operation and >= 60MHz for HS operation.
H A Ddwc3-xilinx.yaml39 - description: Master/Core clock, has to be >= 125 MHz
40 for SS operation and >= 60MHz for HS operation.
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
124 Defines the auto PD disable frequency in MHz.
128 minimum: 1000000 # In case anyone thought this was MHz.
176 minimum: 1000000 # In case anyone thought this was MHz.
223 minimum: 1000000 # In case anyone thought this was MHz.
235 default: 60
283 default: 60
/freebsd/sys/contrib/dev/iwlwifi/fw/
H A Drs.c46 { "60", "64QAM 5/6"},
57 "20Mhz",
58 "40Mhz",
59 "80Mhz",
60 "160 Mhz",
61 "320Mhz",
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsilabs,si5351.txt61 /* 25MHz reference crystal */
71 si5351a: clock-generator@60 {
78 /* connect xtal input to 25MHz reference */
91 * - set initial clock frequency of 74.25MHz
H A Dst,stm32mp25-rcc.yaml36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
103 - description: CK_SCMI_FLEXGEN_60 flexgen clock 60
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Ddove-cubox.dts45 /* 25MHz reference crystal */
90 si5351: clock-generator@60 {
97 /* connect xtal input to 25MHz reference */
/freebsd/sys/contrib/device-tree/Bindings/input/
H A Diqs626a.yaml192 Decreases the internal measurement capacitance from 60 pF to 15 pF.
283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
397 0: 16 MHz (4 MHz)
398 1: 8 MHz (2 MHz)
399 2: 4 MHz (1 MHz)
400 3: 2 MHz (500 kHz)
530 Decreases the internal measurement capacitance from 60 pF to 15 pF.
603 0: 4 MHz (1 MHz)
[all …]
/freebsd/contrib/wpa/hostapd/
H A Dhostapd.conf147 # g = IEEE 802.11g (2.4 GHz), ad = IEEE 802.11ad (60 GHz); a/g options are used
278 #supported_rates=10 20 55 110 60 90 120 180 240 360 480 540
285 #basic_rates=60 120 240
299 # For example, beacon_rate=10 for 1 Mbps or beacon_rate=60 for 6 Mbps (OFDM).
627 # Supported channel width set: [HT40-] = both 20 MHz and 40 MHz with secondary
628 # channel below the primary channel; [HT40+] = both 20 MHz and 40 MHz
630 # (20 MHz only if neither is set)
636 # 5 GHz 40,48,56,64 36,44,52,60
639 # Please note that 40 MHz channels may switch their primary and secondary
640 # channels if needed or creation of 40 MHz channel maybe rejected based
[all …]
/freebsd/contrib/wpa/wpa_supplicant/
H A Dop_classes.c59 * In 80 MHz, the bandwidth "spans" 12 channels (e.g., 36-48), in get_center_80mhz()
129 * In 160 MHz, the bandwidth "spans" 28 channels (e.g., 36-64), in get_center_160mhz()
199 * In 320 MHz, the bandwidth "spans" 60 channels (e.g., 65-125), in get_center_320mhz()
275 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
276 * result and use only the 80 MHz specific version. in verify_channel()
282 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
283 * result and use only the 160 MHz specific version. in verify_channel()
289 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
290 * result and use only the 80 MHz specific version. in verify_channel()
296 * valid 20 MHz channels. Override earlier allow_channel() in verify_channel()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dadi,ad7192.yaml45 pin. If absent, internal 4.92MHz clock is used, which can be made
75 adi,rejection-60-Hz-enable:
77 This bit enables a notch at 60 Hz when the first notch of the sinc
79 60 Hz when the sinc filter first notch is at 50 Hz. This allows
80 simultaneous 50 Hz/ 60 Hz rejection.
204 adi,rejection-60-Hz-enable;

12345678910