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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoV.td60 def simm5 : RISCVSImmLeafOp<5> {
64 return isInt<5>(Imm);
76 [{return (isInt<5>(Imm) && Imm != -16) || Imm == 16;}]> {
82 return (isInt<5>(Imm) && Imm != -16) || Imm == 16;
88 [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
427 // op vd, vs2, vs1, vm
430 (ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
431 opcodestr, "$vd, $vs2, $vs1$vm">;
433 // op vd, vs2, vs1, v0 (without mask, use v0 as carry input)
436 (ins VR:$vs2, VR:$vs1, VMV0:$v0),
[all …]
H A DRISCVInstrFormatsV.td38 class RISCVLSUMOP<bits<5> val> {
39 bits<5> Value = val;
59 bits<5> uimm;
60 bits<5> rd;
76 bits<5> rs1;
77 bits<5> rd;
92 bits<5> rs2;
93 bits<5> rs1;
94 bits<5> rd;
110 bits<5> vs2;
[all …]
H A DRISCVInstrInfoZvk.td18 def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
35 bits<5> vs2;
37 bits<5> vd;
40 let Inst{31-27} = funct6{5-1};
41 let Inst{26} = imm{5};
61 // op vd, vs2, vs1
67 // op vd, vs2, vs1
70 (ins VR:$vd, VR:$vs2, VR:$vs1),
71 opcodestr, "$vd, $vs2, $vs1"> {
95 // op vd, vs2 (use vs1 as instruction encoding) where vd is also a source
[all …]
H A DRISCVInstrInfoXTHead.td58 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
62 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),
63 opcodestr, "$vd, $vs1, $vs2$vm"> {
92 class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>
107 class THRev_r<bits<5> funct5, bits<2> funct2, string opcodestr>
139 class THLoadPair<bits<5> funct5, string opcodestr>
153 class THStorePair<bits<5> funct5, string opcodestr>
164 class THCacheInst_r<bits<5> funct5, string opcodestr>
179 class THCacheInst_void<bits<5> funct5, string opcodestr>
187 class THLoadIndexed<RegisterClass Ty, bits<5> funct5, string opcodestr>
[all …]
/freebsd/crypto/openssl/crypto/perlasm/
H A Driscv.pm108 return 5;
256 my $off5 = ($off + 5);
420 # vadd.vv vd, vs2, vs1, vm
424 my $vs1 = read_vreg shift;
426 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7));
440 # vsub.vv vd, vs2, vs1, vm
444 my $vs1 = read_vreg shift;
446 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7));
550 # vmerge.vvm vd vs2 vs1
554 my $vs1 = read_vreg shift;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-pm8941.dtsi84 <0x0 0x10 5 IRQ_TYPE_EDGE_BOTH>,
224 interrupt-names = "ocp-5vs1", "ocp-5vs2";
233 pm8941_5vs1: 5vs1 {
243 pm8941_5vs2: 5vs2 {
H A Dqcom-apq8084.dtsi110 thermal-sensors = <&tsens 5>;
461 bits = <5 3>;
618 frame-number = <5>;
847 pma8084_5vs1: 5vs1 {};
H A Dqcom-msm8974pro-samsung-klte-common.dtsi46 gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>;
647 pma8084_5vs1: 5vs1 {};
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dqcom,smd-rpm-regulator.yaml55 lvs3, 5vs1, 5vs2
71 l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
114 "^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$":
H A Dqcom,smd-rpm-regulator.txt255 lvs3, 5vs1, 5vs2
270 l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
H A Dmediatek,mt6357-regulator.yaml15 The MT6357 PMIC provides 5 BUCK and 29 LDO.
99 mt6357_vs1_reg: buck-vs1 {
100 regulator-name = "vs1";
H A Dqcom,spmi-regulator.yaml39 "^(5vs[1-2]|(l|s)[1-9][0-9]?|lvs[1-4])$":
161 "^vdd_s[1-5]-supply$": true
220 "^vdd_s[1-5]-supply$": true
276 - description: Over-current protection interrupt for 5V S1
277 - description: Over-current protection interrupt for 5V S2
280 - const: ocp-5vs1
281 - const: ocp-5vs2
409 "^vdd_s[1-5]-supply$": true
H A Dqcom,spmi-regulator.txt212 5vs1, 5vs2
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP7.td92 def P7_FXU_5C : SchedWriteRes<[P7_FXU]> { let Latency = 5; }
H A DPPCInstrMMA.td303 // Defines 5 instructions, unmasked, operand negating.
1061 $vs1, sub_vsx0));
1083 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1085 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
1100 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1102 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
H A DPPCInstrP10.td123 let Inst{0-5} = pref;
136 let TSFlags{5-3} = PPC970_Unit;
152 class VXForm_VTB5_RC<bits<10> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
155 bits<5> VT;
156 bits<5> VB;
170 multiclass VXForm_VTB5_RCr<bits<10> xo, bits<5> R, dag OOL, dag IOL,
187 bits<5> RST;
188 bits<5> RA;
209 bits<5> RT;
210 bits<5> RA;
[all …]
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dspa_stats.c209 seq_printf(f, "%-8s %-16s %-5s %-12s %-12s %-12s " in spa_txg_history_show_header()
249 seq_printf(f, "%-8llu %-16llu %-5c %-12llu " in spa_txg_history_show()
411 vdev_get_stats(spa->spa_root_vdev, &ts->vs1); in spa_txg_history_init_io()
439 ts->vs2.vs_bytes[ZIO_TYPE_READ] - ts->vs1.vs_bytes[ZIO_TYPE_READ], in spa_txg_history_fini_io()
440 ts->vs2.vs_bytes[ZIO_TYPE_WRITE] - ts->vs1.vs_bytes[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
441 ts->vs2.vs_ops[ZIO_TYPE_READ] - ts->vs1.vs_ops[ZIO_TYPE_READ], in spa_txg_history_fini_io()
442 ts->vs2.vs_ops[ZIO_TYPE_WRITE] - ts->vs1.vs_ops[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8186-corsola.dtsi209 pinctrl-5 = <&aud_dat_miso_on>;
417 it6505dptx: dp-bridge@5c {
1296 vsys-vs1-supply = <&pp4200_z2>;
1298 vs1-ldo1-supply = <&mt6366_vs1_reg>;
1364 mt6366_vs1_reg: vs1 {
/freebsd/crypto/openssl/crypto/modes/asm/
H A Daes-gcm-ppc.pl88 # vs1 - vs9 - round keys
116 xxlor 19+32, 5, 5
150 # vs1 - vs9 - round keys
194 xxlor 23+32, 5, 5
286 vpmsumd 27, 5, 18
347 vpmsumd 27, 5, 18
396 vpmsumd 27, 5, 22
424 vpmsumd 24, 5, 28 # H
458 .align 5
510 lxvd2x 5+32, 10, 8 # Hh
[all …]
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaRISCV.cpp522 if ((Val >= 0 && Val <= 3) || (Val >= 5 && Val <= 7)) in CheckLMUL()
745 CheckLMUL(TheCall, 5); in CheckBuiltinFunctionCall()
776 CheckLMUL(TheCall, 5); in CheckBuiltinFunctionCall()
779 // bit_27_26, bit_11_7, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
794 // bit_27_26, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
803 // bit_27_26, vd, vs2, xs1/vs1 in CheckBuiltinFunctionCall()
1322 // 2 <= domain <= 5 in CheckBuiltinFunctionCall()
1324 SemaRef.BuiltinConstantArgRange(TheCall, NumArgs - 1, 2, 5)) in CheckBuiltinFunctionCall()
/freebsd/sys/contrib/openzfs/include/sys/
H A Dspa.h139 * 5 |G| offset3 |
204 * 5 | IV1 |
279 * 5 | payload |
449 #define BP_GET_LEVEL(bp) BF64_GET((bp)->blk_prop, 56, 5)
450 #define BP_SET_LEVEL(bp, x) BF64_SET((bp)->blk_prop, 56, 5, x)
951 TXG_STATE_COMMITTED = 5,
955 vdev_stat_t vs1; member
1194 dmu_tx_t *tx, const char *fmt, ...) __printflike(4, 5);
1196 dmu_tx_t *tx, const char *fmt, ...) __printflike(4, 5);
1198 dmu_tx_t *tx, const char *fmt, ...) __printflike(4, 5);
/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DPPC.cpp830 {{"3"}, "r3"}, {{"4"}, "r4"}, {{"5"}, "r5"},
863 {{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
/freebsd/sys/dev/ixgbe/
H A Dixgbe_type.h549 #define IXGBE_PFVFLRE_INDEX(_i) ((_i) >> 5)
638 #define IXGBE_DMATXCTL_MDP_EN 0x20 /* Bit 5 */
722 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
1026 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
1171 #define IXGBE_FWSM_FW_NVM_RECOVERY_MODE (1 << 5)
1578 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */
1588 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
1647 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */
1648 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
1916 #define IXGBE_RDMAM_WB_COLL_FIFO 5
[all …]
H A Dixgbe_phy.c594 * @device_type: 5 bit device type
676 * @device_type: 5 bit device type
702 * @device_type: 5 bit device type
776 * @device_type: 5 bit device type
834 /* Set or unset auto-negotiation 5G advertisement */ in ixgbe_setup_phy_link_generic()
990 * Reads the VS1 register to determine if link is up and the current speed for
1354 * 5 SFP_SR/LR_CORE0 - 82599-specific in ixgbe_identify_sfp_module_generic()
/freebsd/contrib/ofed/opensm/opensm/
H A Dosm_qos_parser_y.y310 * iser, port-num 900 : 5 #SL for iSER where target port is 900
312 * ipoib, pkey 0x0001 : 5 #SL for IPoIB on partition with pkey 0x0001
338 * port-name: vs1 HCA-1/P1
454 * vlarb-high: 0:255,1:127,2:63,3:31,4:15,5:7,6:3,7:1
506 * sl2vl-table: 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,7

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