Lines Matching +full:5 +full:vs1

58 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
62                    (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),
63                    opcodestr, "$vd, $vs1, $vs2$vm"> {
92 class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>
107 class THRev_r<bits<5> funct5, bits<2> funct2, string opcodestr>
139 class THLoadPair<bits<5> funct5, string opcodestr>
153 class THStorePair<bits<5> funct5, string opcodestr>
164 class THCacheInst_r<bits<5> funct5, string opcodestr>
179 class THCacheInst_void<bits<5> funct5, string opcodestr>
187 class THLoadIndexed<RegisterClass Ty, bits<5> funct5, string opcodestr>
196 class THLoadUpdate<bits<5> funct5, string opcodestr>
200   bits<5> simm5;
210 class THStoreIndexed<RegisterClass StTy, bits<5> funct5, string opcodestr>
219 class THStoreUpdate<bits<5> funct5, string opcodestr>
223   bits<5> simm5;