| /linux/drivers/comedi/drivers/ |
| H A D | ni_labpc_regs.h | 17 #define STAT1_GATA0 BIT(5)
19 #define CMD1_REG 0x00 /* W: Command 1 reg */
24 #define CMD2_REG 0x01 /* W: Command 2 reg */
30 #define CMD2_2SDAC1 BIT(5)
32 #define CMD3_REG 0x02 /* W: Command 3 reg */
38 #define CMD3_FIFOINTEN BIT(5)
39 #define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */
40 #define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */
41 #define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */
42 #define ADC_FIFO_CLEAR_REG 0x08 /* W: A/D FIFO Clear reg */
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| H A D | icp_multi.c | 24 * 12-bit resolution. Ranges : 5V, 10V, +/-5V, +/-10V, 0..20mA and 4..20mA.
28 * There are 4 x 12-bit Analogue Outputs. Ranges : 5V, 10V, +/-5V, +/-10V
41 #define ICP_MULTI_ADC_CSR 0x00 /* R/W: ADC command/status register */
45 #define ICP_MULTI_ADC_CSR_RA BIT(5) /* Input range 0 = 5V, 1 = 10V */
50 #define ICP_MULTI_DAC_CSR 0x04 /* R/W: DAC command/status register */
54 #define ICP_MULTI_DAC_CSR_RA BIT(5) /* Output range 0 = 5V, 1 = 10V */
56 #define ICP_MULTI_AO 6 /* R/W: Analogue output data */
57 #define ICP_MULTI_DI 8 /* R/W: Digital inputs */
58 #define ICP_MULTI_DO 0x0A /* R/W: Digital outputs */
59 #define ICP_MULTI_INT_EN 0x0c /* R/W: Interrupt enable register */
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| /linux/drivers/scsi/ |
| H A D | nsp32.h | 37 MODEL_PCI_LOGITEC = 5,
81 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
82 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
88 # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
112 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
113 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
119 # define NO_TRANSFER_TO_HOST BIT(5)
130 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
132 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
136 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
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| H A D | fdomain.h | 16 #define REG_SCSI_DATA 0 /* R/W: SCSI Data (with ACK) */
23 #define BSTAT_SEL BIT(5) /* Select */
26 #define REG_BCTL 1 /* W: SCSI Bus Control */
32 #define BCTL_CMD BIT(5) /* Command/Data */
41 #define ASTAT_FIFOEN BIT(5) /* FIFO enabled */
44 #define REG_ICTL 2 /* W: Interrupt Control */
47 #define ICTL_ARB BIT(5) /* Int. on Arbitration complete */
55 #define REG_MCTL 3 /* W: SCSI Data Mode Control */
58 #define MCTL_TARGET BIT(5) /* Enable target mode */
66 #define IRQ_RST BIT(5) /* SCSI Reset interrupt */
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| /linux/arch/loongarch/vdso/ |
| H A D | vgetrandom-chacha.S | 93 REG_S s5, sp, SZREG * 5
99 li.w copy0, 0x61707865
100 li.w copy1, 0x3320646e
101 li.w copy2, 0x79622d32
103 ld.w cnt_lo, counter, 0
104 ld.w cnt_hi, counter, 4
111 li.w state3, 0x6b206574
113 /* state[4,5,..,11] = key */
114 ld.w state4, key, 0
115 ld.w state5, key, 4
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| /linux/arch/powerpc/crypto/ |
| H A D | sha1-powerpc-asm.S | 26 #define RT(t) ((((t)+5)%6)+7)
33 /* We use registers 16 - 31 for the W values */
34 #define W(t) (((t)%16)+16) macro
37 LWZ(W(t),(t)*4,r4)
42 rotlwi RT(t),RA(t),5; \
46 add r14,r0,W(t); \
47 LWZ(W((t)+4),((t)+4)*4,r4); \
54 rotlwi RT(t),RA(t),5; \
58 xor r5,W((t)+4-3),W((t)+4-8); \
60 xor W((t)+4),W((t)+4-16),W((t)+4-14); \
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| H A D | sha1-spe-asm.S | 107 LOAD_DATA(w0, off) /* 1: W */ \
111 rotrwi rT0,a,27; /* 1: A' = A rotl 5 */ \
115 add e,e,w0; /* 1: E = E + W */ \
116 LOAD_DATA(w1, off+4) /* 2: W */ \
123 rotrwi rT0,e,27; /* 2: A' = A rotl 5 */ \
124 add d,d,w1; /* 2: E = E + W */ \
127 evmergelo w1,w1,w0; /* mix W[0]/W[1] */ \
132 evmergelohi rT0,w7,w6; /* W[-3] */ \
134 evxor w0,w0,rT0; /* W = W[-16] xor W[-3] */ \
136 evxor w0,w0,w4; /* W = W xor W[-8] */ \
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| /linux/arch/loongarch/lib/ |
| H A D | memcpy.S | 54 .align 5
57 slli.d a2, a2, 5
61 .align 5
64 .align 5
69 .align 5
74 .align 5
81 .align 5
82 4: ld.w t0, a1, 0
83 st.w t0, a0, 0
86 .align 5
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| H A D | copy_user.S | 80 5: ld.d t3, a1, 24
138 .align 5
141 slli.d a3, a2, 5
145 .align 5
149 .align 5
155 .align 5
161 .align 5
169 .align 5
170 42: ld.w t0, a1, 0
171 43: st.w t0, a0, 0
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| /linux/lib/crypto/ |
| H A D | sha256.c | 54 static inline void LOAD_OP(int I, u32 *W, const u8 *input) in LOAD_OP() argument
56 W[I] = get_unaligned_be32((__u32 *)input + I); in LOAD_OP()
59 static inline void BLEND_OP(int I, u32 *W) in BLEND_OP() argument
61 W[I] = s1(W[I-2]) + W[I-7] + s0(W[I-15]) + W[I-16]; in BLEND_OP()
66 t1 = h + e1(e) + Ch(e, f, g) + SHA256_K[i] + W[i]; \
72 static void sha256_transform(u32 *state, const u8 *input, u32 *W) in sha256_transform() argument
79 LOAD_OP(i + 0, W, input); in sha256_transform()
80 LOAD_OP(i + 1, W, input); in sha256_transform()
81 LOAD_OP(i + 2, W, input); in sha256_transform()
82 LOAD_OP(i + 3, W, input); in sha256_transform()
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| /linux/Documentation/driver-api/media/drivers/ |
| H A D | tuners.rst | 38 5: With FM
69 MF: BG LL w/ Secam (Multi France)
75 MK3 series introduced in 2002 w/ PHILIPS_MK3_API
81 4[01][0136][269]F[HYNR]5
82 40x2: Tuner (5V/33V), TEMIC_API.
83 40x6: Tuner 5V
91 F[HYNR]5
95 FR5: w/ FM radio
101 - TPI8NSR11 : NTSC J/M (TPI8NSR01 w/FM) (P,210/497)
102 - TPI8PSB11 : PAL B/G (TPI8PSB01 w/FM) (P,170/450)
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| /linux/arch/x86/crypto/ |
| H A D | sha512-ssse3-asm.S | 99 # W[t]+K[t] (stack frame)
126 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
130 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
132 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
139 ror $5, tmp0 # 39 # tmp = a ror 5
140 xor a_64, tmp0 # tmp = (a ror 5) ^ a
142 ror $6, tmp0 # 34 # tmp = ((a ror 5) ^ a) ror 6
143 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a
155 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
156 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
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| H A D | sha512-avx-asm.S | 78 # W[t] + K[t] | W[t+1] + K[t+1]
101 # W[t]+K[t] (stack frame)
132 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
136 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
138 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
145 RORQ tmp0, 5 # 39 # tmp = a ror 5
146 xor a_64, tmp0 # tmp = (a ror 5) ^ a
148 RORQ tmp0, 6 # 34 # tmp = ((a ror 5) ^ a) ror 6
149 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a
160 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
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| H A D | sha1_ssse3_asm.S | 62 /* we keep window of 64 w[i]+K pre-calculated values in a circular buffer */
250 * RR does two rounds of SHA-1 back to back with W[] pre-calc
251 * t1 = F(b, c, d); e += w(i)
252 * e += t1; b <<= 30; d += w(i+1);
254 * d += t1; a <<= 5;
257 * t1 <<= 5;
270 rol $5, \a
273 ror $7, \a # (a <<r 5) >>r 7) => a <<r 30)
278 rol $5, T1
312 .set W, W0 define
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| /linux/drivers/input/gameport/ |
| H A D | fm801-gp.c | 31 unsigned short w; in fm801_gp_cooked_read() local
33 w = inw(gameport->io + 2); in fm801_gp_cooked_read()
34 *buttons = (~w >> 14) & 0x03; in fm801_gp_cooked_read()
35 axes[0] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
36 w = inw(gameport->io + 4); in fm801_gp_cooked_read()
37 axes[1] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
38 w = inw(gameport->io + 6); in fm801_gp_cooked_read()
39 *buttons |= ((~w >> 14) & 0x03) << 2; in fm801_gp_cooked_read()
40 axes[2] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
41 w = inw(gameport->io + 8); in fm801_gp_cooked_read()
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| /linux/drivers/net/fddi/skfp/h/ |
| H A D | supern_2.h | 55 #define FS_SFRMTY1 (1<<5) /* frame-type bit (impementor) */
67 #define FRM_LLCS (5)
147 #define RD_FRM_LLCS (unsigned long)(5<<20)
235 * FORMAC+ read/write (r/w) registers
243 #define FM_IMSK1U 0x04 /* r/w upper 16-bit of IMSK 1 */
244 #define FM_IMSK1L 0x05 /* r/w lower 16-bit of IMSK 1 */
245 #define FM_IMSK2U 0x06 /* r/w upper 16-bit of IMSK 2 */
246 #define FM_IMSK2L 0x07 /* r/w lower 16-bit of IMSK 2 */
247 #define FM_SAID 0x08 /* r/w short addr.-individual */
248 #define FM_LAIM 0x09 /* r/w long addr.-ind. (MSW of LAID) */
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| /linux/arch/mips/kernel/ |
| H A D | r4k-bugs64.c | 3 * Copyright (C) 2003, 2004, 2007 Maciej W. Rozycki
44 void mult_sh_align_mod(long *v1, long *v2, long *w, in mult_sh_align_mod() argument
73 : "0" (5), "1" (8), "2" (5)); in mult_sh_align_mod()
87 "dsll32 %0, %4, %5\n\t" in mult_sh_align_mod()
89 "dsll32 %1, %4, %5\n\t" in mult_sh_align_mod()
116 *w = lw; in mult_sh_align_mod()
121 long v1[8], v2[8], w[8]; in check_mult_sh() local
135 mult_sh_align_mod(&v1[0], &v2[0], &w[0], 32, 0); in check_mult_sh()
136 mult_sh_align_mod(&v1[1], &v2[1], &w[1], 32, 1); in check_mult_sh()
137 mult_sh_align_mod(&v1[2], &v2[2], &w[2], 32, 2); in check_mult_sh()
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| /linux/drivers/net/ethernet/marvell/ |
| H A D | skge.h | 141 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
156 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
199 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
225 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
242 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
306 GP_IO_5 = 1<<5, /* IO_5 pin */
397 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
421 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
430 * Bank 4 - 5
520 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
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| /linux/tools/testing/selftests/net/ |
| H A D | test_bridge_neigh_suppress.sh | 276 sleep 5
305 run_cmd "ip netns exec $h1 arping -q -b -c 1 -w 5 -s $sip -I eth0.$vid $tip"
316 run_cmd "ip netns exec $h1 arping -q -b -c 1 -w 5 -s $sip -I eth0.$vid $tip"
327 run_cmd "ip netns exec $h1 arping -q -b -c 1 -w 5 -s $sip -I eth0.$vid $tip"
337 run_cmd "ip netns exec $h1 arping -q -b -c 1 -w 5 -s $sip -I eth0.$vid $tip"
347 run_cmd "ip netns exec $h1 arping -q -b -c 1 -w 5 -s $sip -I eth0.$vid $tip"
361 run_cmd "ip netns exec $h1 arping -q -b -c 1 -w 5 -s $sip -I eth0.$vid $tip"
371 run_cmd "ip netns exec $h1 arping -q -b -c 1 -w 5 -s $sip -I eth0.$vid $tip"
373 tc_check_packets $sw1 "dev vx0 egress" 101 5
408 run_cmd "ip netns exec $h1 ndisc6 -q -r 1 -s $saddr -w 5000 $daddr eth0.$vid"
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| /linux/arch/arm/boot/dts/st/ |
| H A D | stih407-pinctrl.dtsi | 11 /* 0-5: PIO_SBC */
146 rx = <&pio3 5 ALT1 IN>;
164 scl = <&pio4 5 ALT1 BIDIR>;
182 keyin1 = <&pio4 5 ALT4 IN>;
209 txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
212 rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
244 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
253 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
268 txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
273 rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>;
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| /linux/include/video/ |
| H A D | pm3fb.h | 62 #define PM3ByApertureMode_PIXELSIZE_8BIT (0 << 5)
63 #define PM3ByApertureMode_PIXELSIZE_16BIT (1 << 5)
64 #define PM3ByApertureMode_PIXELSIZE_32BIT (2 << 5)
65 #define PM3ByApertureMode_PIXELSIZE_MASK (3 << 5)
79 #define PM3ByApertureMode_DOUBLE_WRITE_16MB (5 << 22)
124 #define PM3VideoControl_VSYNC_FORCE_HIGH (0 << 5)
125 #define PM3VideoControl_VSYNC_ACTIVE_HIGH (1 << 5)
126 #define PM3VideoControl_VSYNC_FORCE_LOW (2 << 5)
127 #define PM3VideoControl_VSYNC_ACTIVE_LOW (3 << 5)
128 #define PM3VideoControl_VSYNC_MASK (3 << 5)
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| /linux/drivers/scsi/pcmcia/ |
| H A D | nsp_cs.h | 51 #define IRQSTATUS 0x00 /* W */
57 #define IFSELECT 0x01 /* W */
66 #define INDEXREG 0x02 /* R/W */
67 #define DATAREG 0x03 /* R/W */
68 #define FIFODATA 0x04 /* R/W */
69 #define FIFODATA1 0x05 /* R/W */
70 #define FIFODATA2 0x06 /* R/W */
71 #define FIFODATA3 0x07 /* R/W */
76 #define EXTBUSCTRL 0x10 /* R/W,deleted */
78 #define CLOCKDIV 0x11 /* R/W */
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| /linux/arch/m68k/math-emu/ |
| H A D | fp_util.S | 106 move.w #0x3fff+31,%d1
134 lsr.w #8,%d1
136 cmp.w #0xff,%d1 | NaN / Inf?
139 add.w #0x3fff-0x7f,%d1 | re-bias the exponent.
152 move.w #0x4000-0x7f,%d1
157 move.w #0x7fff,%d1
172 lsr.w #5,%d1
174 cmp.w #0x7ff,%d1 | NaN / Inf?
177 add.w #0x3fff-0x3ff,%d1 | re-bias the exponent.
197 move.w #0x4000-0x3ff,%d1
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| /linux/sound/mips/ |
| H A D | ad1843.c | 39 ad1843_RSS = { 2, 5, 3 }, /* Right ADC Source Select */
43 ad1843_RD2M = { 3, 0, 5 }, /* Right DAC 2 Mix Gain/Atten */
45 ad1843_LD2M = { 3, 8, 5 }, /* Left DAC 2 Mix Gain/Atten */
47 ad1843_RX1M = { 4, 0, 5 }, /* Right Aux 1 Mix Gain/Atten */
49 ad1843_LX1M = { 4, 8, 5 }, /* Left Aux 1 Mix Gain/Atten */
51 ad1843_RX2M = { 5, 0, 5 }, /* Right Aux 2 Mix Gain/Atten */
52 ad1843_RX2MM = { 5, 7, 1 }, /* Right Aux 2 Mix Mute */
53 ad1843_LX2M = { 5, 8, 5 }, /* Left Aux 2 Mix Gain/Atten */
54 ad1843_LX2MM = { 5, 15, 1 }, /* Left Aux 2 Mix Mute */
55 ad1843_RMCM = { 7, 0, 5 }, /* Right Mic Mix Gain/Atten */
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| /linux/include/uapi/linux/ |
| H A D | switchtec_ioctl.h | 27 #define SWITCHTEC_IOCTL_PART_VENDOR0 5
87 #define SWITCHTEC_IOCTL_EVENT_FW_NMI 5
124 #define SWITCHTEC_IOCTL_EVENT_FLAG_DIS_POLL (1 << 5)
136 __u32 data[5];
147 _IOR('W', 0x40, struct switchtec_ioctl_flash_info)
149 _IOWR('W', 0x41, struct switchtec_ioctl_flash_part_info)
151 _IOR('W', 0x42, struct switchtec_ioctl_event_summary)
153 _IOR('W', 0x42, struct switchtec_ioctl_event_summary_legacy)
155 _IOWR('W', 0x43, struct switchtec_ioctl_event_ctl)
157 _IOWR('W', 0x44, struct switchtec_ioctl_pff_port)
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