Lines Matching +full:5 +full:w

29  *	from: @(#)ns16550.h	7.1 (Berkeley) 5/9/91
39 #define	com_data	0	/* data register (R/W) */
42 #define	com_ier		1	/* interrupt enable register (W) */
65 #define	com_lcr		3	/* line control register (R/W) */
66 #define	com_cfcr	com_lcr	/* character format control register (R/W) */
95 #define	com_mcr		4	/* modem control register (R/W) */
105 #define	MCR_BITS	"\20\1DTR\2RTS\3DRS\4IE\5LOOPBACK\10PRESCALE"
107 #define	com_lsr		5	/* line status register (R/W) */
121 #define	LSR_BITS	"\20\1RXRDY\2OE\3PE\4FE\5BI\6THRE\7TEMT\10RCV_FIFO"
123 #define	com_msr		6	/* modem status register (R/W) */
134 #define	MSR_BITS	"\20\1DCTS\2DDSR\3TERI\4DDCD\5CTS\6DSR\7RI\10DCD"
137 #define	com_dll		0	/* divisor latch low (R/W) */
139 #define	com_dlm		1	/* divisor latch high (R/W) */
145 #define	com_scr		7	/* scratch register (R/W) */
148 #define	com_fcr		2	/* FIFO control register (W) */
172 #define	com_efr		2	/* enhanced features register (R/W) */
180 #define	com_xon1	4	/* XON 1 character (R/W) */
181 #define	com_xon2	5	/* XON 2 character (R/W) */
182 #define	com_xoff1	6	/* XOFF 1 character (R/W) */
183 #define	com_xoff2	7	/* XOFF 2 character (R/W) */
192 #define	com_asr		1	/* additional status register (R[0-7]/W[0-1]) */
194 /* 16950 register #3.  R/W access enabled by ACR[7]. */
204  * 16950 register #5.  Accessible if !LCR_EFR_ENABLE.  Read access also
207 #define	com_icr		5	/* index control register (R/W) */
214 #define	com_spr		com_scr	/* scratch pad (and index) register (R/W) */
222 #define	com_acr		0	/* additional control register (R/W) */
227 #define	com_cpr		1	/* clock prescaler register (R/W) */
228 #define	com_tcr		2	/* times clock register (R/W) */
229 #define	com_ttl		4	/* transmitter trigger level (R/W) */
230 #define	com_rtl		5	/* receiver trigger level (R/W) */