| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | armada3700-periph-clock.txt | 14 -----------------------------------
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
43 7 gbe1-core Gigabit Ethernet core port 1
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| H A D | marvell,armada-3700-periph-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/marvell,armada-3700-periph-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
22 -----------------------------------
44 -----------------------------------
45 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
46 1 gbe-core parent clock for Gigabit Ethernet core
[all …]
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| H A D | starfive,jh7100-clkgen.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
11 - Emil Renner Berthing <kernel@esmil.dk>
15 const: starfive,jh7100-clkgen
22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
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| H A D | rockchip,rk3528-cru.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yao Zi <ziyao@disroot.org>
18 the clock. All available clock and reset IDs are defined in dt-binding
23 const: rockchip,rk3528-cru
30 - description: External 24MHz oscillator clock
31 - description: >
32 50MHz clock generated by PHY module, for generating GMAC0 clocks only.
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| H A D | st,stm32mp25-rcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
17 include/dt-bindings/clock/st,stm32mp25-rcc.h
18 include/dt-bindings/reset/st,stm32mp25-rcc.h
23 - st,stm32mp25-rcc
28 '#clock-cells':
31 '#reset-cells':
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | ti,dp83822.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
39 ti,fiber-mode:
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| H A D | nxp,tja11xx.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
[all …]
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| H A D | micrel.txt | 7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
34 - clocks, clock-names: contains clocks according to the common clock bindings.
37 - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference
40 - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode
[all …]
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| H A D | stm32-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
26 - st,stm32mp25-dwmac
[all …]
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| H A D | rockchip-dwmac.txt | 6 - compatible: should be "rockchip,<name>-gamc"
7 "rockchip,px30-gmac": found on PX30 SoCs
8 "rockchip,rk3128-gmac": found on RK312x SoCs
9 "rockchip,rk3228-gmac": found on RK322x SoCs
10 "rockchip,rk3288-gmac": found on RK3288 SoCs
11 "rockchip,rk3328-gmac": found on RK3328 SoCs
12 "rockchip,rk3366-gmac": found on RK3366 SoCs
13 "rockchip,rk3368-gmac": found on RK3368 SoCs
14 "rockchip,rk3399-gmac": found on RK3399 SoCs
15 "rockchip,rv1108-gmac": found on RV1108 SoCs
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/ |
| H A D | stmpe.txt | 2 ----------------
5 - compatible: "st,stmpe-ts"
8 - st,ave-ctrl : Sample average control
9 0 -> 1 sample
10 1 -> 2 samples
11 2 -> 4 samples
12 3 -> 8 samples
13 - st,touch-det-delay : Touch detect interrupt delay (recommended is 3)
14 0 -> 10 us
15 1 -> 50 us
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| /freebsd/sys/contrib/dev/iwlwifi/mvm/ |
| H A D | rfi.c | 1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2020 - 2022 Intel Corporation
8 #include "fw/api/phy-ctxt.h"
11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
16 {cpu_to_le16(160), {50, 5
[all...] |
| /freebsd/sys/dev/sfxge/common/ |
| H A D | ef10_tlv_layout.h | 1 /*-
2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
48 * systems which are little-endian and do not do strange things with structure
49 * padding. (Big-endian host systems will require some byte-swapping.)
51 * -----
53 * Please refer to SF-108797-SW for a general overview of the TLV partition
56 * -----
62 * - L is a location, indicating where this tag is expected to be found:
69 * - TTT is a type, which is just a unique value. The same type value
73 * - NNNN is an index of some form. Some item types are per-port, some
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_radio.c | 28 0x101479e, /* Freq 2412 - (128 << 17) + 83870 */
29 0x101d027, /* Freq 2417 - (128 << 17) + 118823 */
30 0x10258af, /* Freq 2422 - (129 << 17) + 22703 */
31 0x102e138, /* Freq 2427 - (129 << 17) + 57656 */
32 0x10369c0, /* Freq 2432 - (129 << 17) + 92608 */
33 0x103f249, /* Freq 2437 - (129 << 17) + 127561 */
34 0x1047ad1, /* Freq 2442 - (130 << 17) + 31441 */
35 0x105035a, /* Freq 2447 - (130 << 17) + 66394 */
36 0x1058be2, /* Freq 2452 - (130 << 17) + 101346 */
37 0x106146b, /* Freq 2457 - (131 << 17) + 5227 */
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | am5729-beagleboneai.dts | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
9 #include "am57xx-commercial-grade.dtsi"
10 #include "dra74x-mmc-iodelay.dtsi"
11 #include "dra74-ipu-dsp-common.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/pinctrl/dra.h>
18 compatible = "beagle,am5729-beagleboneai", "ti,am5728",
[all …]
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| /freebsd/sys/arm/freescale/imx/ |
| H A D | imx6_anatop.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 * kitchen-sinked this device, not us. :)
46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes
52 * are deci-Celsius, which are converted to/from deci-Kelvins in the sysctl
81 { -1, 0 }
119 * 396MHz, it also says that the ARM and SOC voltages can't differ by
124 uint32_t mhz; member
136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
141 #define TZ_ZEROC 2731 /* deci-Kelvin <-> deci-Celsius offset. */
[all …]
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| /freebsd/contrib/wpa/wpa_supplicant/ |
| H A D | op_classes.c | 6 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 for (i = 0; i < mode->num_channels; i++) { in allow_channel()
30 chan_is_6ghz = is_6ghz_freq(mode->channels[i].freq); in allow_channel()
31 if (is_6ghz == chan_is_6ghz && mode->channels[i].chan == chan) in allow_channel()
35 if (i == mode->num_channels || in allow_channel()
36 (mode->channels[i].flag & HOSTAPD_CHAN_DISABLED)) in allow_channel()
40 *flags = mode->channels[i].flag; in allow_channel()
42 if (mode->channels[i].flag & HOSTAPD_CHAN_NO_IR) in allow_channel()
54 if (mode->mode != HOSTAPD_MODE_IEEE80211A) in get_center_80mhz()
59 * In 80 MHz, the bandwidth "spans" 12 channels (e.g., 36-48), in get_center_80mhz()
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | sony,imx335.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul J. Murphy <paul.j.murphy@intel.com>
12 - Daniele Alessandrelli <daniele.alessandrelli@intel.com>
18 sent through MIPI CSI-2.
28 description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz
31 avdd-supply:
34 ovdd-supply:
37 dvdd-supply:
[all …]
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| /freebsd/sys/dts/arm/ |
| H A D | zybo.dts | 1 /*-
27 /dts-v1/;
28 /include/ "zynq-7000.dtsi"
32 compatible = "digilent,zybo", "xlnx,zynq-7000";
47 clock-frequency = <50000000>; // 50Mhz PS_CLK
51 clock-frequency = <325000000>; // 325Mhz
67 spi-chipselect = <0>;
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| /freebsd/sys/contrib/device-tree/src/powerpc/ |
| H A D | ac14xx.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #address-cells = <1>;
15 #size-cells = <1>;
26 timebase-frequency = <40000000>; /* 40 MHz (csb/4) */
27 bus-frequency = <160000000>; /* 160 MHz csb bus */
28 clock-frequency = <400000000>; /* 400 MHz ppc core */
49 compatible = "cfi-flash";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 bank-width = <2>;
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| /freebsd/sys/contrib/dev/athk/ |
| H A D | dfs_pattern_detector.c | 25 * struct radar_types - contains array of patterns defined for one DFS domain
37 #define MIN_PPB_THRESH 50
38 #define PPB_THRESH_RATE(PPB, RATE) ((PPB * RATE + 100 - RATE) / 100)
43 #define WIDTH_LOWER(X) ((X*(100-WIDTH_TOLERANCE)+50)/100)
44 #define WIDTH_UPPER(X) ((X*(100+WIDTH_TOLERANCE)+50)/100)
49 (PRF2PRI(PMAX) - PRI_TOLERANCE), \
54 /* radar types as defined by ETSI EN-301-893 v1.5.1 */
74 PMIN - PRI_TOLERANCE, \
93 FCC_PATTERN(5, 50, 100, 1000, 2000, 1, 1, true),
106 PMIN - PRI_TOLERANCE, \
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | sdhci-st.txt | 1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | intel,pinctrl-keembay.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
19 const: intel,keembay-pinctrl
24 gpio-controller: true
26 '#gpio-cells':
39 interrupt-controller: true
41 '#interrupt-cells':
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | spear_smi.txt | 4 - compatible : "st,spear600-smi"
5 - reg : Address range of the mtd chip
6 - #address-cells, #size-cells : Must be present if the device has sub-nodes
8 - interrupts: Should contain the STMMAC interrupts
9 - clock-rate : Functional clock rate of SMI in Hz
12 - st,smi-fast-mode : Flash supports read in fast mode
17 compatible = "st,spear600-smi";
18 #address-cells = <1>;
19 #size-cells = <1>;
21 interrupt-parent = <&vic1>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | jcore,spi.txt | 1 J-Core SPI master
5 - compatible: Must be "jcore,spi2".
7 - reg: Memory region for registers.
9 - #address-cells: Must be 1.
11 - #size-cells: Must be 0.
15 - clocks: If a phandle named "ref_clk" is present, SPI clock speed
18 fixed 50 MHz.
20 - clock-names: Clock names, one for each phandle in clocks.
22 See spi-bus.txt for additional properties not specific to this device.
28 #address-cells = <1>;
[all …]
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