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/linux/drivers/staging/greybus/Documentation/
H A Dsysfs-bus-greybus3 KernelVersion: 4.XX
11 KernelVersion: 4.XX
18 KernelVersion: 4.XX
26 KernelVersion: 4.XX
34 KernelVersion: 4.XX
42 KernelVersion: 4.XX
49 KernelVersion: 4.XX
57 KernelVersion: 4.XX
64 KernelVersion: 4.XX
72 KernelVersion: 4.XX
[all …]
/linux/include/uapi/linux/
H A Dserial_reg.h30 * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
62 * PC16550D: 1 4 8 14 xx xx xx xx
63 * TI16C550A: 1 4 8 14 xx xx xx xx
64 * TI16C550C: 1 4 8 14 xx xx xx xx
65 * ST16C550: 1 4 8 14 xx xx xx xx
67 * NS16C552: 1 4 8 14 xx xx xx xx
69 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
72 * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA
85 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
90 #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
[all …]
/linux/arch/powerpc/platforms/
H A DKconfig.cputype20 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their
21 embedded 512x/52xx/82xx/83xx/86xx counterparts.
22 The other embedded parts, namely 4xx, 8xx and e500
23 (85xx) each form a family of their own that is not compatible
26 If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx.
29 bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx"
35 bool "Freescale 85xx"
39 bool "Freescale 8xx"
208 bool "8xx family"
223 bool "G4 (74xx)"
[all …]
H A DKconfig8 source "arch/powerpc/platforms/52xx/Kconfig"
14 source "arch/powerpc/platforms/8xx/Kconfig"
15 source "arch/powerpc/platforms/82xx/Kconfig"
16 source "arch/powerpc/platforms/83xx/Kconfig"
17 source "arch/powerpc/platforms/85xx/Kconfig"
18 source "arch/powerpc/platforms/86xx/Kconfig"
82 interrupt controller provides less than 4 interrupts to each
83 cpu. This will enable the generic code to multiplex the 4
210 temperature within 2-4 degrees Celsius. This option shows the current
235 G4's). If the range is small (around 4 degrees), the temperature is
/linux/arch/powerpc/boot/dts/
H A Diss4xx-mpic.dts22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
36 model = "PowerPC,4xx"; // real CPU changed in sim
50 model = "PowerPC,4xx"; // real CPU changed in sim
66 model = "PowerPC,4xx"; // real CPU changed in sim
82 model = "PowerPC,4xx"; // real CPU changed in sim
115 compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
122 compatible = "ibm,opb-4xx", "ibm,opb";
H A Diss4xx.dts20 model = "ibm,iss-4xx";
21 compatible = "ibm,iss-4xx";
34 model = "PowerPC,4xx"; // real CPU changed in sim
53 compatible = "ibm,uic-4xx", "ibm,uic";
64 compatible = "ibm,uic-4xx", "ibm,uic";
76 compatible = "ibm,plb-4xx", "ibm,plb4"; /* Could be PLB6, doesn't matter */
83 compatible = "ibm,opb-4xx", "ibm,opb";
/linux/include/sound/
H A Dminors.h24 #define SNDRV_MINOR_HWDEP 4 /* 4 - 7 */
54 #define SNDRV_MINOR_HWDEPS 4
62 #define SNDRV_MINOR_OSS_CARD(minor) ((minor) >> 4)
64 #define SNDRV_MINOR_OSS(card, dev) (((card) << 4) | (dev))
66 #define SNDRV_MINOR_OSS_MIXER 0 /* /dev/mixer - OSS 3.XX compatible */
67 #define SNDRV_MINOR_OSS_SEQUENCER 1 /* /dev/sequencer - OSS 3.XX compatible */
68 #define SNDRV_MINOR_OSS_MIDI 2 /* /dev/midi - native midi interface - OSS 3.XX compatible - UART */
70 #define SNDRV_MINOR_OSS_PCM_8 3 /* /dev/dsp - 8bit PCM - OSS 3.XX compatible */
71 #define SNDRV_MINOR_OSS_AUDIO 4 /* /dev/audio - SunSparc compatible */
72 #define SNDRV_MINOR_OSS_PCM_16 5 /* /dev/dsp16 - 16bit PCM - OSS 3.XX compatible */
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,pef2256.yaml83 enum: [0, 1, 2, 3, 4, 5, 6, 7]
92 For instance, suppose lantiq,data-rate-bps = 8192000 (ie 4*2048000), and
94 (nu) and used time-slots (XX) for TSi is
95 nu nu XX nu nu nu XX nu nu nu XX nu
99 nu XX nu nu nu XX nu nu nu XX nu nu
103 nu XX nu XX nu XX
192 dai-tdm-slot-num = <4>;
194 /* TS 1, 2, 3, 4 */
206 dai-tdm-slot-num = <4>;
/linux/Documentation/devicetree/bindings/watchdog/
H A Dmpc8xxx-wdt.txt1 * Freescale mpc8xxx watchdog driver (For 83xx, 86xx and 8xx)
10 On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
11 On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
12 On the 8xx, "General System Interface Unit" area: <0x0 0x10>
15 - reg: additional physical address and length (4) of location of the
17 On the 83xx, it is located at offset 0x910
18 On the 86xx, it is located at offset 0xe0094
19 On the 8xx, it is located at offset 0x288
/linux/arch/arm/mach-omap2/
H A Dprm2xxx_3xxx.h134 /* Named PM_EVEGENONTIM_MPU on the 24XX */
139 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
144 /* Named PRCM_CLKSSETUP on the 24XX */
149 /* Named PRCM_CLKSRC_CTRL on the 24XX */
166 /* Named RM_RSTTIME_WKUP on the 24xx */
173 /* Named RM_RSTCTRL_WKUP on the 24xx */
187 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
196 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
205 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
206 * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
[all …]
H A Dpowerdomain-common.c16 #include "cm-regbits-34xx.h"
17 #include "prm-regbits-34xx.h"
18 #include "prm-regbits-44xx.h"
58 case 4: in omap2_pwrdm_get_mem_bank_onstate_mask()
78 case 4: in omap2_pwrdm_get_mem_bank_retst_mask()
98 case 4: in omap2_pwrdm_get_mem_bank_stst_mask()
H A Dsoc.h40 #define OMAP2_DEVICE_TYPE_BAD 4
48 * SoC class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
140 IS_OMAP_CLASS(24xx, 0x24)
141 IS_OMAP_CLASS(34xx, 0x34)
142 IS_OMAP_CLASS(44xx, 0x44)
143 IS_AM_CLASS(35xx, 0x35)
144 IS_OMAP_CLASS(54xx, 0x54)
145 IS_AM_CLASS(33xx, 0x33)
146 IS_AM_CLASS(43xx, 0x43)
148 IS_TI_CLASS(81xx, 0x81)
[all …]
H A Dclock.h28 #define RATE_IN_36XX (1 << 4)
40 /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
/linux/include/net/
H A D6lowpan.h81 /* SCI/DCI is 4 bit width, so we have maximum 16 entries */
82 #define LOWPAN_IPHC_CTX_TABLE_SIZE (1 << 4)
229 * addr: xx xx xx xx xx xx
230 * addr: xx xx xx xx xx xx
274 /* First bit of addr is multicast, reserved or 802.15.4 specific */ in lowpan_802154_is_valid_src_short_addr()
/linux/lib/
H A Dnet_utils.c13 /* XX:XX:XX:XX:XX:XX */ in mac_pton()
25 mac[i] = (hex_to_bin(s[i * 3]) << 4) | hex_to_bin(s[i * 3 + 1]); in mac_pton()
/linux/arch/arm/mach-orion5x/
H A Dtsx09-common.c77 return (hi << 4) | lo; in qnap_tsx09_parse_hex_byte()
89 * Enforce "xx:xx:xx:xx:xx:xx\n" format. in qnap_tsx09_check_mac_addr()
110 * (format "xx:xx:xx:xx:xx:xx\n").
/linux/arch/powerpc/mm/book3s32/
H A Dmmu_context.c5 * architecture specification. This includes the 6xx, 7xx, 7xxx,
6 * and 8260 implementations but excludes the 8xx and 4xx.
33 * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
129 mtspr(SPRN_SDR1, rol32(__pa(next->pgd), 4) & 0xffff01ff); in switch_mmu_context()
/linux/arch/powerpc/include/asm/
H A Dtime.h54 * The 4xx doesn't even have a decrementer. I tried to use the
55 * generic timer interrupt code, which seems OK, with the 4xx PIT
65 * Note: Book E and 4xx processors differ from other PowerPC processors
67 * transition for Book E/4xx, but on the 0 to -1 transition for others.
/linux/drivers/usb/core/
H A Ddevices.c55 "\nT: Bus=%2.2d Lev=%2.2d Prnt=%2.2d Port=%2.2d Cnt=%2.2d Dev#=%3d Spd=%-4s MxCh=%2d\n";
72 /* B: Alloc=ddd/ddd us (xx%), #Int=ddd, #Iso=ddd */
76 /* D: Ver=xx.xx Cls=xx(sssss) Sub=xx Prot=xx MxPS=dd #Cfgs=dd */
80 /* P: Vendor=xxxx ProdID=xxxx Rev=xx.xx */
84 /* C: #Ifs=dd Cfg#=dd Atr=xx MPwr=dddmA */
88 /* A: FirstIf#=dd IfCount=dd Cls=xx(sssss) Sub=xx Prot=xx */
92 /* I: If#=dd Alt=dd #EPs=dd Cls=xx(sssss) Sub=xx Prot=xx Driver=xxxx*/
96 /* E: Ad=xx(s) Atr=xx(ssss) MxPS=dddd Ivl=D?s */
97 "E: Ad=%02x(%c) Atr=%02x(%-4s) MxPS=%4d Ivl=%d%cs\n";
/linux/Documentation/scsi/
H A Dg_NCR5380.rst37 irq=xx[,...] the interrupt(s)
38 base=xx[,...] the port or base address(es) (for port or memory mapped, resp.)
39 card=xx[,...] card type(s):
46 4 Hewlett Packard C2502
53 ncr_irq=xx the interrupt
54 ncr_addr=xx the port or base address (for port or memory
90 modprobe g_NCR5380 irq=0,7 base=0x240,0x300 card=3,4
/linux/drivers/scsi/qla2xxx/
H A Dqla_target.h250 #define ATIO_TYPE7 0x06 /* Accept target I/O entry for 24xx */
301 #define FCP_CMND_TASK_MGMT_LU_RESET 4
309 * add_cdb is optional and can absent from struct atio7_fcp_cmnd. Size 4
313 uint8_t add_cdb[4];
346 uint8_t fcp_cmnd_len_high:4;
347 uint8_t attr:4;
387 return get_unaligned_be32(&atio->u.isp24.fcp_cmnd.add_cdb[len * 4]); in get_datalen_for_atio()
390 #define CTIO_TYPE7 0x12 /* Continue target I/O entry (for 24xx) */
393 * ISP queue - Continue Target I/O (ATIO) type 7 entry (for 24xx) structure.
394 * This structure is sent to the ISP 24xx from the target driver.
[all …]
/linux/arch/arm/probes/kprobes/
H A Dcheckers-thumb.c37 /* xx | Rn | Rt | | Rm |*/ in t32_check_stack()
38 /* STR (register) 1111 1000 0100 xxxx xxxx 0000 00xx xxxx */ in t32_check_stack()
39 /* STRB (register) 1111 1000 0000 xxxx xxxx 0000 00xx xxxx */ in t32_check_stack()
40 /* STRH (register) 1111 1000 0010 xxxx xxxx 0000 00xx xxxx */ in t32_check_stack()
41 /* INVALID INSN 1111 1000 0110 xxxx xxxx 0000 00xx xxxx */ in t32_check_stack()
47 /* xx | Rn | Rt | PUW| imm8 |*/ in t32_check_stack()
92 asi->stack_space = hweight32(reglist) * 4; in t16_check_stack()
/linux/drivers/net/ethernet/cavium/liquidio/
H A Docteon_config.h54 (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
56 (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
61 #define DEFAULT_NUM_NIC_PORTS_68XX 4
98 #define CN23XX_MAX_MACS 4
106 #define OCTEON_MAX_BASE_IOQ 4
113 #define DEF_TXQS_PER_INTF 4
114 #define DEF_RXQS_PER_INTF 4
181 LIO_210SV = 0, /* Two port, 66xx */
182 LIO_210NV, /* Two port, 68xx */
183 LIO_410NV, /* Four port, 68xx */
[all …]
/linux/Documentation/devicetree/bindings/powerpc/
H A Dibm,powerpc-cpu-features.txt213 usable-privilege = <1 | 2 | 4>;
214 hwcap-bit-nr = <xx>;
221 hwcap-bit-nr = <xx>;
226 usable-privilege = <2 | 4>;
233 usable-privilege = <1 | 2 | 4>;
236 hwcap-bit-nr = <xx>;
241 usable-privilege = <1 | 2 | 4>;
243 fscr-bit-nr = <xx>;
244 hwcap-bit-nr = <xx>;
/linux/include/clocksource/
H A Dtimer-ti-dm.h120 #define WP_TMAR (1 << 4)
129 #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
130 #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
131 #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
132 #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
133 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
134 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */

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