1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2543d9378SPaul Walmsley /* 3543d9378SPaul Walmsley * linux/arch/arm/mach-omap2/clock.h 4543d9378SPaul Walmsley * 5d8a94458SPaul Walmsley * Copyright (C) 2005-2009 Texas Instruments, Inc. 6530e544fSPaul Walmsley * Copyright (C) 2004-2011 Nokia Corporation 7a16e9703STony Lindgren * 8a16e9703STony Lindgren * Contacts: 9543d9378SPaul Walmsley * Richard Woodruff <r-woodruff2@ti.com> 10543d9378SPaul Walmsley * Paul Walmsley 11543d9378SPaul Walmsley */ 12543d9378SPaul Walmsley 13543d9378SPaul Walmsley #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H 14543d9378SPaul Walmsley #define __ARCH_ARM_MACH_OMAP2_CLOCK_H 15543d9378SPaul Walmsley 1612706c54SPaul Walmsley #include <linux/kernel.h> 17a135eaaeSPaul Walmsley #include <linux/list.h> 1812706c54SPaul Walmsley 19e10dd62fSPaul Walmsley #include <linux/clkdev.h> 20f9ae32a7SMike Turquette #include <linux/clk-provider.h> 21f38b0dd6STero Kristo #include <linux/clk/ti.h> 22e10dd62fSPaul Walmsley 23a135eaaeSPaul Walmsley /* struct clksel_rate.flags possibilities */ 24a135eaaeSPaul Walmsley #define RATE_IN_242X (1 << 0) 25a135eaaeSPaul Walmsley #define RATE_IN_243X (1 << 1) 26a135eaaeSPaul Walmsley #define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */ 27a135eaaeSPaul Walmsley #define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */ 28a135eaaeSPaul Walmsley #define RATE_IN_36XX (1 << 4) 29a135eaaeSPaul Walmsley #define RATE_IN_4430 (1 << 5) 30a135eaaeSPaul Walmsley #define RATE_IN_TI816X (1 << 6) 31a135eaaeSPaul Walmsley #define RATE_IN_4460 (1 << 7) 32a135eaaeSPaul Walmsley #define RATE_IN_AM33XX (1 << 8) 33a135eaaeSPaul Walmsley #define RATE_IN_TI814X (1 << 9) 34a135eaaeSPaul Walmsley 35a135eaaeSPaul Walmsley #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) 36a135eaaeSPaul Walmsley #define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS) 37a135eaaeSPaul Walmsley #define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX) 38a135eaaeSPaul Walmsley #define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460) 39a135eaaeSPaul Walmsley 40a135eaaeSPaul Walmsley /* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */ 41a135eaaeSPaul Walmsley #define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX) 42a135eaaeSPaul Walmsley 43c0bf3132SRussell King /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 44c0bf3132SRussell King #define CORE_CLK_SRC_32K 0x0 45c0bf3132SRussell King #define CORE_CLK_SRC_DPLL 0x1 46c0bf3132SRussell King #define CORE_CLK_SRC_DPLL_X2 0x2 47c0bf3132SRussell King 48c0bf3132SRussell King /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ 49c0bf3132SRussell King #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 50c0bf3132SRussell King #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 51c0bf3132SRussell King #define OMAP2XXX_EN_DPLL_LOCKED 0x3 52c0bf3132SRussell King 53c0bf3132SRussell King /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ 54c0bf3132SRussell King #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 55c0bf3132SRussell King #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 56c0bf3132SRussell King #define OMAP3XXX_EN_DPLL_LOCKED 0x7 57c0bf3132SRussell King 5816975a79SRajendra Nayak /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ 5916975a79SRajendra Nayak #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 6016975a79SRajendra Nayak #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 6116975a79SRajendra Nayak #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 6216975a79SRajendra Nayak #define OMAP4XXX_EN_DPLL_LOCKED 0x7 6316975a79SRajendra Nayak 646c0afb50STero Kristo extern struct ti_clk_ll_ops omap_clk_ll_ops; 656c0afb50STero Kristo 66e9e63088STero Kristo int __init omap2_clk_setup_ll_ops(void); 679f029b15STero Kristo 688111e010STero Kristo void __init ti_clk_init_features(void); 69543d9378SPaul Walmsley #endif 70