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/linux/drivers/gpio/
H A Dgpio-104-idi-48.c3 * GPIO driver for the ACCES 104-IDI-48 family
6 * This driver supports the following ACCES devices: 104-IDI-48A,
7 * 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
29 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
34 MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
49 *mask = BIT(line); in idi_48_reg_mask_xlate()
87 #define IDI48_NGPIO 48
91 .mask = BIT((_id) / 8), \
115 "Bit 0 A", "Bit 1 A", "Bit 2 A", "Bit 3 A", "Bit 4 A", "Bit 5 A",
116 "Bit 6 A", "Bit 7 A", "Bit 8 A", "Bit 9 A", "Bit 10 A", "Bit 11 A",
[all …]
/linux/include/uapi/linux/
H A Ddccp.h13 * @dccph_doff - Data Offset from the start of the DCCP header, in 32-bit words
17 * @dccph_x - 0 = 24 bit sequence number, 1 = 48
51 * struct dccp_hdr_ext - the low bits of a 48 bit seq packet
53 * @dccph_seq_low - low 24 bits of a 48 bit seq packet
70 * @dccph_resp_ack_nr_high - 48 bit ack number high order bits, contains GSR
71 * @dccph_resp_ack_nr_low - 48 bit ack number low order bits, contains GSR
81 * @dccph_resp_ack - 48 bit Acknowledgment Number Subheader (5.3)
92 * @dccph_reset_ack - 48 bit Acknowledgment Number Subheader (5.6)
H A Dhdreg.h153 #define WIN_READ 0x20 /* 28-Bit */
154 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
155 #define WIN_READ_LONG 0x22 /* 28-Bit */
156 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
157 #define WIN_READ_EXT 0x24 /* 48-Bit */
158 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
159 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
160 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
164 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
168 #define WIN_WRITE 0x30 /* 28-Bit */
[all …]
/linux/lib/crc/arm/
H A Dcrc-t10dif-core.S116 * Pairwise long polynomial multiplication of two 16-bit values
120 * by two 64-bit values
125 * significant. The resulting 80-bit vectors are XOR'ed together.
139 * 6 (w0*x6 ^ w1*x5) << 48 ^ | (y0*z6 ^ y1*z5) << 48 ^
148 * and after performing 8x8->16 bit long polynomial multiplication of
150 * we obtain the following four vectors of 16-bit elements:
161 * final 80-bit result.
231 // the bit order match the polynomial coefficient order.
340 // Convert to 8-bit masks: 'len' 0x00 bytes, then '16-len' 0xff bytes.
388 // Reduce the 128-bit value M(x), stored in q7, to the final 16-bit CRC.
[all …]
/linux/Documentation/sound/cards/
H A Daudiophile-usb.rst52 Please exit any audio application running before switching between bit depths
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
66 * 24-bit/96kHz ==> 2 channels in _or_ 2 channels out (half duplex only)
113 24bit-depth-mode and immediately after wants to switch to a 16bit-depth mode,
132 supported audio format are S16_BE for 16-bit depth modes and S24_3BE for
190 16-bit modes
197 - 16bits 48kHz mode with Di disabled
204 - 16bits 48kHz mode with Di enabled
227 24-bit modes
[all …]
/linux/arch/powerpc/kernel/vdso/
H A Dsigtramp32.S65 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
97 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
108 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
138 #define VREGS 48*RSIZE+34*8
180 rsave (32, 48*RSIZE + 0*8); \
181 rsave (33, 48*RSIZE + 1*8); \
182 rsave (34, 48*RSIZE + 2*8); \
183 rsave (35, 48*RSIZE + 3*8); \
184 rsave (36, 48*RSIZE + 4*8); \
185 rsave (37, 48*RSIZE + 5*8); \
[all …]
H A Dsigtramp64.S70 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
103 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
114 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
155 #define VREGS 48*RSIZE+33*8
204 rsave (32, 48*RSIZE + 0*8); \
205 rsave (33, 48*RSIZE + 1*8); \
206 rsave (34, 48*RSIZE + 2*8); \
207 rsave (35, 48*RSIZE + 3*8); \
208 rsave (36, 48*RSIZE + 4*8); \
209 rsave (37, 48*RSIZE + 5*8); \
[all …]
/linux/lib/crc/x86/
H A Dcrc-pclmul-consts.h11 * CRC folding constants generated for most-significant-bit-first CRC-16 using
21 u8 shuf_table[48];
26 0xdccf000000000000, /* LO64_TERMS: (x^2000 mod G) * x^48 */
27 0x4b0b000000000000, /* HI64_TERMS: (x^2064 mod G) * x^48 */
30 0x9d9d000000000000, /* LO64_TERMS: (x^976 mod G) * x^48 */
31 0x7cf5000000000000, /* HI64_TERMS: (x^1040 mod G) * x^48 */
34 0x044c000000000000, /* LO64_TERMS: (x^464 mod G) * x^48 */
35 0xe658000000000000, /* HI64_TERMS: (x^528 mod G) * x^48 */
38 0x6ee3000000000000, /* LO64_TERMS: (x^208 mod G) * x^48 */
39 0xe7b5000000000000, /* HI64_TERMS: (x^272 mod G) * x^48 */
[all …]
/linux/drivers/net/ethernet/microsoft/mana/
H A Dshm_channel.c75 /* Poll the hardware for the ownership bit. This should be pretty fast, in mana_smc_poll_register()
87 if (!(last_dword & BIT(31))) in mana_smc_poll_register()
171 * 52-bit frame addresses are split into the lower 48 bits and upper in mana_smc_setup_hwc()
172 * 4 bits. Lower 48 bits of 4 address are written sequentially from in mana_smc_setup_hwc()
173 * the start of the 256-bit shared memory region followed by 16 bits in mana_smc_setup_hwc()
176 * A 16 bit EQ vector number fills out the next-to-last 32-bit dword. in mana_smc_setup_hwc()
178 * The final 32-bit dword is used for protocol control information as in mana_smc_setup_hwc()
185 /* EQ addr: low 48 bits of frame address */ in mana_smc_setup_hwc()
193 /* CQ addr: low 48 bits of frame address */ in mana_smc_setup_hwc()
201 /* RQ addr: low 48 bits of frame address */ in mana_smc_setup_hwc()
[all …]
/linux/sound/pci/emu10k1/
H A Dp16v.h73 * [19:16] Playback mixer output enable. 1 bit per channel.
74 * [23:20] Capture mixer output enable. 1 bit per channel.
94 * 1 - 48 khz
112 /* Start Playback [3:0] (one bit per channel)
113 * Start Capture [11:8] (one bit per channel)
130 * bit 0x1 starts DMA playback on channel_id 0
135 #define WATERMARK 0x46 /* Test bit to indicate cache level usage */
147 /* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
148 /* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
174 /* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
[all …]
/linux/arch/mips/loongson64/
H A Ddma.c10 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in phys_to_dma()
11 * Loongson-3's 48bit address space and embed it into 40bit */ in phys_to_dma()
19 /* We extract 2bit node id (bit 44~47, only bit 44~45 used now) from in dma_to_phys()
20 * Loongson-3's 48bit address space and embed it into 40bit */ in dma_to_phys()
/linux/arch/alpha/kernel/
H A Dsys_wildfire.c243 * Bit Meaning
259 *48 Interrupt Line A from slot 4 PCI1
279 * 1 64 bit PCI 0 option slot 1 (SCSI QLogic builtin)
280 * 2 64 bit PCI 0 option slot 2
281 * 3 64 bit PCI 0 option slot 3
282 * 4 64 bit PCI 1 option slot 4
283 * 5 64 bit PCI 1 option slot 5
284 * 6 64 bit PCI 1 option slot 6
285 * 7 64 bit PCI 1 option slot 7
297 { 48, 48, 48+1, 48+2, 48+3}, /* IdSel 4 PCI 1 slot 4 */ in wildfire_map_irq()
/linux/drivers/reset/
H A Dreset-eic7700.c25 #define CLEAR_BOOT_FLAG_BIT BIT(0)
47 u32 bit; member
56 #define EIC7700_RESET(id, reg, bit)[id] = \ argument
57 { SYSCRG_RESET_OFFSET + (reg) * sizeof(u32), BIT(bit) }
59 /* mapping table for reset ID to register offset and reset bit */
272 EIC7700_RESET(EIC7700_RESET_TIMER0_0, 48, 0),
273 EIC7700_RESET(EIC7700_RESET_TIMER0_1, 48, 1),
274 EIC7700_RESET(EIC7700_RESET_TIMER0_2, 48, 2),
275 EIC7700_RESET(EIC7700_RESET_TIMER0_3, 48, 3),
276 EIC7700_RESET(EIC7700_RESET_TIMER0_4, 48, 4),
[all …]
/linux/drivers/net/dsa/b53/
H A Db53_regs.h67 /* Port Control Register (8 bit) */
69 #define PORT_CTRL_RX_DISABLE BIT(0)
70 #define PORT_CTRL_TX_DISABLE BIT(1)
71 #define PORT_CTRL_RX_BCST_EN BIT(2) /* Broadcast RX (P8 only) */
72 #define PORT_CTRL_RX_MCST_EN BIT(3) /* Multicast RX (P8 only) */
73 #define PORT_CTRL_RX_UCST_EN BIT(4) /* Unicast RX (P8 only) */
83 /* SMP Control Register (8 bit) */
86 /* Switch Mode Control Register (8 bit) */
88 #define SM_SW_FWD_MODE BIT(0) /* 1 = Managed Mode */
89 #define SM_SW_FWD_EN BIT(1) /* Forwarding Enable */
[all …]
/linux/drivers/gpu/drm/xe/
H A Dxe_lmtt_ml.c17 * LMHAW (Local Memory Host Address Width) is 48 bit (256TB)
19 * LMGAW (Local Memory Guest Address Width) is 48 bit (256TB)
58 #define LMTT_ML_HAW 48 /* 256 TiB */
62 #define LMTT_ML_PDE_VALID BIT(0)
67 #define LMTT_ML_PTE_MAX_NUM BIT(35 - ilog2(SZ_2M))
69 #define LMTT_ML_PTE_VALID BIT(0)
82 BUILD_BUG_ON(LMTT_ML_HAW == 48 && LMTT_ML_PDE_L2_MAX_NUM != SZ_8K); in lmtt_ml_pte_num()
/linux/include/soc/fsl/
H A Dbman.h34 /* wrapper for 48-bit buffers */
39 __be16 hi; /* High 16-bits of 48-bit address */
40 __be32 lo; /* Low 32-bits of 48-bit address */
46 * Restore the 48 bit address previously stored in BMan
/linux/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_hw.h41 #define OVERWRITE BIT(31)
42 #define IS_BUFFER_POOL BIT(20)
43 #define PREFETCH_BUF_EN BIT(21)
92 #define ACCEPTLERR BIT(19)
93 #define QCOHERENT BIT(4)
94 #define RECOMBBUF BIT(27)
137 #define BUSY_MASK BIT(0)
138 #define READ_CYCLE_MASK BIT(0)
150 #define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
151 #define RESUME_TX BIT(0)
[all …]
/linux/drivers/crypto/marvell/octeontx/
H A Dotx_cpt_hw_types.h46 #define OTX_CPT_VF_INTR_MBOX_MASK BIT(0)
47 #define OTX_CPT_VF_INTR_DOVF_MASK BIT(1)
48 #define OTX_CPT_VF_INTR_IRDE_MASK BIT(2)
49 #define OTX_CPT_VF_INTR_NWRP_MASK BIT(3)
50 #define OTX_CPT_VF_INTR_SERR_MASK BIT(4)
181 * sign-extended bit <48> for forward compatibility.
197 * use a sign-extended bit <48> for forward compatibility.
255 * doneint:1 [16:16] Done interrupt. This bit is copied from the
290 * This register has the BIST status of memories. Each bit is the BIST result
291 * of an individual memory (per bit, 0 = pass and 1 = fail).
[all …]
/linux/arch/powerpc/lib/
H A Dchecksum_64.S19 * and adds in "sum" (32-bit).
86 ld r15,48(r3)
113 ld r15,48(r3)
176 rldicl r4,r0,32,0 /* fold two 32 bit halves together */
205 * and adds in 0xffffffff (32-bit), while copying the block to dst.
279 source; ld r15,48(r3)
296 dest; std r15,48(r4)
315 source; ld r15,48(r3)
332 dest; std r15,48(r4)
398 rldicl r4,r0,32,0 /* fold two 32 bit halves together */
[all …]
/linux/arch/parisc/kernel/
H A Dsignal32.h11 /* 32-bit ucontext as seen from an 64-bit kernel */
25 * 64-bit registers in a non-portable, non-ABI, hidden structure.
31 /* Upper half of all the 64-bit registers that were truncated
32 on a copy to a 32-bit userspace */
48 * The 32-bit ABI wants at least 48 bytes for a function call frame:
54 #define FUNCTIONCALLFRAME32 48
/linux/drivers/net/ethernet/sfc/
H A Dmae_counter_format.h19 * ER_RX_SL_PACKETISER_HEADER_WORD(160bit):
41 #define ERF_SC_PACKETISER_HEADER_COUNT_LBN 48
53 * ER_RX_SL_PACKETISER_PAYLOAD_WORD(128bit):
66 #define ERF_SC_PACKETISER_PAYLOAD_PACKET_COUNT_WIDTH 48
70 #define ERF_SC_PACKETISER_PAYLOAD_BYTE_COUNT_WIDTH 48
/linux/drivers/crypto/cavium/cpt/
H A Dcpt_hw_types.h44 * sign-extended bit <48> for forward compatibility.
60 * use a sign-extended bit <48> for forward compatibility.
117 * doneint:1 [16:16] Done interrupt. This bit is copied from the
152 * This register has the BIST status of memories. Each bit is the BIST result
153 * of an individual memory (per bit, 0 = pass and 1 = fail).
156 * bstatus [29:0](RO/H) BIST status. One bit per memory, enumerated by
213 * This register has the BIST status of each engine. Each bit is the
214 * BIST result of an individual engine (per bit, 0 = pass and 1 = fail).
217 * reserved_48_63:16 [63:48] reserved
218 * bstatus:48 [47:0](RO/H) BIST status. One bit per engine.
[all …]
/linux/drivers/clk/pxa/
H A Dclk-pxa3xx.c58 * Clock Enable Bit
94 #define CKEN_MINI_IM 48 /* < Mini-IM */
100 /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
199 return (parent_rate / 48) * smcfs_mult[(acsr >> 23) & 0x7] / in clk_pxa3xx_smemc_get_rate()
220 #define CKEN_AB(bit) ((CKEN_ ## bit > 31) ? CKENB : CKENA) argument
222 div_hp, bit, is_lp, flags) \ argument
223 PXA_CKEN(dev_id, con_id, bit, parents, mult_lp, div_lp, \
224 mult_hp, div_hp, is_lp, CKEN_AB(bit), \
225 (CKEN_ ## bit % 32), flags)
226 #define PXA3XX_PBUS_CKEN(dev_id, con_id, bit, mult_lp, div_lp, \ argument
[all …]
/linux/lib/842/
H A D842_compress.c54 { I2, I2, D4, N0, 0x0f }, /* 48 */
55 { I2, D2, I2, D2, 0x0c }, /* 48 */
56 { I2, D4, I2, N0, 0x0b }, /* 48 */
57 { D2, I2, I2, D2, 0x07 }, /* 48 */
58 { D2, I2, D2, I2, 0x06 }, /* 48 */
59 { D4, I2, I2, N0, 0x03 }, /* 48 */
94 u8 bit; member
169 int b = p->bit, bits = b + n, s = round_up(bits, 8) - bits; in add_bits()
178 /* split this up if writing to > 8 bytes (i.e. n == 64 && p->bit > 0), in add_bits()
204 else if (bits <= 48) in add_bits()
[all...]
/linux/Documentation/arch/m68k/
H A Dbuddha-driver.rst30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
32 $48, while it doesn't matter how often you're writing to $4a
33 as long as $48 is not touched. After $48 has been written,
35 address just written. Make sure $4a is written before $48,
66 $f00 read only, Byte-access: Bit 7 shows the
71 $f40 read only, Byte-access: Bit 7 shows the
76 $f80 read only, Byte-access: Bit 7 shows the
131 only the upper three bits are used (Bits 7 to 5). Bit 4
173 the timing will always be mode 0 8-bit compatible, no matter
190 clock cycle is shortened to a bit less than 70ns (not worth

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