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Searched +full:400 +full:mhz (Results 1 – 25 of 208) sorted by relevance

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/linux/drivers/clk/mvebu/
H A Dmv98dx3236.c25 * 0 = 400 MHz 400 MHz 800 MHz
26 * 2 = 667 MHz 667 MHz 2000 MHz
27 * 3 = 800 MHz 800 MHz 1600 MHz
34 * 1 = 667 MHz 667 MHz 2000 MHz
35 * 2 = 400 MHz 400 MHz 400 MHz
36 * 3 = 800 MHz 800 MHz 800 MHz
37 * 5 = 800 MHz 400 MHz 800 MHz
46 /* Tclk = 200MHz, no SaR dependency */ in mv98dx3236_get_tclk_freq()
H A Darmada-375.c29 * 6 = 400 MHz 400 MHz 200 MHz
30 * 15 = 600 MHz 600 MHz 300 MHz
31 * 21 = 800 MHz 534 MHz 400 MHz
32 * 25 = 1000 MHz 500 MHz 500 MHz
36 * 0 = 166 MHz
37 * 1 = 200 MHz
H A Ddove.c26 * 5 = 1000 MHz
27 * 6 = 933 MHz
28 * 7 = 933 MHz
29 * 8 = 800 MHz
30 * 9 = 800 MHz
31 * 10 = 800 MHz
32 * 11 = 1067 MHz
33 * 12 = 667 MHz
34 * 13 = 533 MHz
35 * 14 = 400 MHz
[all …]
H A Dap806-system-controller.c56 *dclk_freq = 400; in ap806_get_sar_clocks()
68 *dclk_freq = 400; in ap806_get_sar_clocks()
72 *dclk_freq = 400; in ap806_get_sar_clocks()
80 *dclk_freq = 400; in ap806_get_sar_clocks()
88 *dclk_freq = 400; in ap806_get_sar_clocks()
92 *dclk_freq = 400; in ap806_get_sar_clocks()
96 *dclk_freq = 400; in ap806_get_sar_clocks()
191 /* Fixed clock is always 1200 Mhz */ in ap806_syscon_common_probe()
/linux/drivers/i3c/master/mipi-i3c-hci/
H A Dxfer_mode_rate.h48 #define XFERRATE_I3C_SDR0 0x00 /* 12.5 MHz */
49 #define XFERRATE_I3C_SDR1 0x01 /* 8 MHz */
50 #define XFERRATE_I3C_SDR2 0x02 /* 6 MHz */
51 #define XFERRATE_I3C_SDR3 0x03 /* 4 MHz */
52 #define XFERRATE_I3C_SDR4 0x04 /* 2 MHz */
53 #define XFERRATE_I3C_SDR_FM_FMP 0x05 /* 400 KHz / 1 MHz */
57 #define XFERRATE_I2C_FM 0x00 /* 400 KHz */
58 #define XFERRATE_I2C_FMP 0x01 /* 1 MHz */
/linux/drivers/clk/mediatek/
H A Dclk-mt8365-apmixedsys.c15 #define MT8365_PLL_FMAX (3800UL * MHZ)
16 #define MT8365_PLL_FMIN (1500UL * MHZ)
57 { .div = 1, .freq = 1500 * MHZ },
58 { .div = 2, .freq = 750 * MHZ },
59 { .div = 3, .freq = 375 * MHZ },
66 { .div = 1, .freq = 1600 * MHZ },
67 { .div = 2, .freq = 800 * MHZ },
68 { .div = 3, .freq = 400 * MHZ },
69 { .div = 4, .freq = 200 * MHZ },
75 { .div = 1, .freq = 1600 * MHZ },
[all …]
H A Dclk-mt8183-apmixedsys.c51 #define MT8183_PLL_FMAX (3800UL * MHZ)
52 #define MT8183_PLL_FMIN (1500UL * MHZ)
94 { .div = 1, .freq = 1500 * MHZ },
95 { .div = 2, .freq = 750 * MHZ },
96 { .div = 3, .freq = 375 * MHZ },
103 { .div = 1, .freq = 1600 * MHZ },
104 { .div = 2, .freq = 800 * MHZ },
105 { .div = 3, .freq = 400 * MHZ },
106 { .div = 4, .freq = 200 * MHZ },
/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h20 * HP9000/300 and /400 models (BI_HP300_MODEL)
25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
[all …]
/linux/drivers/memory/
H A Djedec_ddr_data.c33 /* Speed bin 400(200 MHz) */
54 /* Speed bin 533(266 MHz) */
75 /* Speed bin 800(400 MHz) */
96 /* Speed bin 1066(533 MHz) */
/linux/drivers/video/fbdev/aty/
H A Dmach64_gx.c17 #define REF_FREQ_2595 1432 /* 14.33 MHz (exact 14.31818) */
20 #define MAX_FREQ_2595 15938 /* 159.38 MHz (really 170.486) */
21 #define MIN_FREQ_2595 8000 /* 80.00 MHz ( 85.565) */
23 #define ABS_MIN_FREQ_2595 1000 /* 10.00 MHz (really 10.697) */
136 8000, (3 << 6) | 20, 9}, /* 7395 ps / 135.2273 MHz */ in aty_var_to_pll_514()
138 10000, (1 << 6) | 19, 3}, /* 9977 ps / 100.2273 MHz */ in aty_var_to_pll_514()
140 13000, (1 << 6) | 2, 3}, /* 12509 ps / 79.9432 MHz */ in aty_var_to_pll_514()
142 14000, (2 << 6) | 8, 7}, /* 13394 ps / 74.6591 MHz */ in aty_var_to_pll_514()
144 16000, (1 << 6) | 44, 6}, /* 15378 ps / 65.0284 MHz */ in aty_var_to_pll_514()
146 25000, (1 << 6) | 15, 5}, /* 17460 ps / 57.2727 MHz */ in aty_var_to_pll_514()
[all …]
/linux/drivers/net/wireless/ath/wcn36xx/
H A Dtxrx.c134 /* 11ac 20 MHz 800ns GI MCS 0-8 */
156 /* 11ac 20 MHz 400ns SGI MCS 6-8 */
166 /* 11ac 40 MHz 800ns GI MCS 0-9 */
187 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
195 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
202 /* 11ac 80 MHz 800ns GI MCS 0-7 */
215 /* 11ac 80 MHz 800 ns GI MCS 8-9 */
228 /* 11ac 80 MHz 400 ns SGI MCS 6-7 */
235 /* 11ac 80 MHz 400ns SGI MCS 8-9 */
/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.h30 /* UMD PState Vangogh Msg Parameters in MHz */
43 #define VANGOGH_UMD_PSTATE_MIN_SCLK_GFXCLK 400
51 #define VANGOGH_UMD_PSTATE_MIN_MCLK_FCLK 400
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca15_a7.dts44 capacity-dmips-mhz = <1024>;
54 capacity-dmips-mhz = <1024>;
64 capacity-dmips-mhz = <516>;
74 capacity-dmips-mhz = <516>;
84 capacity-dmips-mhz = <516>;
162 compatible = "arm,cci-400";
169 compatible = "arm,cci-400-ctrl-if";
175 compatible = "arm,cci-400-ctrl-if";
181 compatible = "arm,cci-400-pmu,r0";
245 /* Reference 24MHz clock */
/linux/Documentation/devicetree/bindings/sound/
H A Dnuvoton,nau8325.yaml47 and FS are within the range. MCLK range is from 2.048MHz to 24.576MHz.
49 MCLK_SRC/LRCK of 256, 400 or 500, and needs to detect the BCLK
/linux/drivers/clocksource/
H A Dtimer-rtl-otto.c44 * Timers are derived from the lexra bus (LXB) clock frequency. This is 175 MHz
45 * on RTL930x and 200 MHz on the other platforms. With 3.125 MHz choose a common
207 .rating = 400,
234 .rating = 400,
/linux/Documentation/devicetree/bindings/input/
H A Diqs269a.yaml180 0: 16 MHz (4 MHz)
181 1: 8 MHz (2 MHz)
182 2: 4 MHz (1 MHz)
183 3: 2 MHz (500 kHz)
248 default: 400
389 0: 4 MHz (1 MHz)
390 1: 2 MHz (500 kHz)
391 2: 1 MHz (250 kHz)
580 azoteq,timeout-tap-ms = <400>;
/linux/Documentation/devicetree/bindings/display/imx/
H A Dnxp,imx8mq-dcss.yaml73 - description: Must be 800 MHz
74 - description: Must be 400 MHz
/linux/drivers/media/radio/
H A Dlm7000.h28 freq += 171200; /* Add 10.7 MHz IF */ in lm7000_set_freq()
29 freq /= 400; /* Convert to 25 kHz units */ in lm7000_set_freq()
/linux/drivers/i2c/busses/
H A Di2c-stm32.h20 STM32_I2C_SPEED_FAST, /* 400 kHz */
21 STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */
H A Di2c-designware-common.c205 * Only standard mode at 100kHz, fast mode at 400kHz, in i2c_dw_validate_speed()
206 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported. in i2c_dw_validate_speed()
214 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n", in i2c_dw_validate_speed()
531 * transfer supported by the driver (for 400KHz this is in __i2c_dw_disable()
560 * transfer supported by the driver (for 400kHz this is in __i2c_dw_disable()
/linux/drivers/gpu/drm/gma500/
H A Doaktrail.h132 u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
133 /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
/linux/Documentation/dev-tools/
H A Dgpio-sloppy-logic-analyzer.rst67 snippet which analyzes an I2C bus at 400kHz on a Renesas Salvator-XS board, the
70 parameter. The bus speed is 400kHz. So, the sampling theorem says we need to
73 ``-s 1500000`` for 1.5MHz. Also, we don't want to sample right away but wait
/linux/drivers/watchdog/
H A Drc32434_wdt.c53 * safe for CPU clock speeds up to 400MHz, as
54 * ((2 ^ 32) - 1) / (400MHz / 2) = 21s. */
/linux/Documentation/i2c/busses/
H A Di2c-nforce2.rst7 * nForce2 Ultra 400 MCP 10de:0084
39 Flags: 66Mhz, fast devsel, IRQ 5
/linux/drivers/clk/renesas/
H A Drzg2l-cpg.c207 * As per the HW manual, we should not directly switch from 533 MHz to in rzg2l_cpg_sd_clk_mux_notifier()
208 * 400 MHz and vice versa. To change the setting from 2’b01 (533 MHz) in rzg2l_cpg_sd_clk_mux_notifier()
209 * to 2’b10 (400 MHz) or vice versa, Switch to 2’b11 (266 MHz) first, in rzg2l_cpg_sd_clk_mux_notifier()
210 * and then switch to the target setting (2’b01 (533 MHz) or 2’b10 in rzg2l_cpg_sd_clk_mux_notifier()
211 * (400 MHz)). in rzg2l_cpg_sd_clk_mux_notifier()
214 * The clock mux has 3 input clocks(533 MHz, 400 MHz, and 266 MHz), and in rzg2l_cpg_sd_clk_mux_notifier()
257 * 1/ SD div cannot be 1 (val == 0) if parent rate is 800MHz in rzg3s_cpg_div_clk_notifier()
258 * 2/ OCTA / SPI div cannot be 1 (val == 0) if parent rate is 400MHz in rzg3s_cpg_div_clk_notifier()
259 * As SD can have only one parent having 800MHz and OCTA div can have in rzg3s_cpg_div_clk_notifier()
260 * only one parent having 400MHz we took into account the parent rate in rzg3s_cpg_div_clk_notifier()

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