Home
last modified time | relevance | path

Searched +full:4 +full:- +full:cpu (Results 1 – 25 of 1093) sorted by relevance

12345678910>>...44

/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip07.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
H A Dhip06.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/
H A Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/cavium/
H A Dthunder-88xx.dtsi2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
63 #size-cells = <0>;
[all …]
/freebsd/share/man/man4/
H A Dsmp.424 .Dd January 4, 2019
29 .Nd description of the FreeBSD Symmetric Multi-Processor kernel
35 kernel implements symmetric multi-processor support.
43 the read-only sysctl variable
46 The number of online threads per CPU core is available in the read-only sysctl
49 The number of physical CPU cores detected by the system is available in the
50 read-only sysctl variable
54 allows specific CPUs on a multi-processor system to be disabled.
57 tunable, where X is the APIC ID of a CPU.
58 Setting this tunable to 1 will result in the corresponding CPU being
[all …]
H A Dcpufreq.425 .Dd April 4, 2022
30 .Nd CPU frequency control framework
56 driver provides a unified kernel and user interface to CPU frequency
79 configured P-state.)
87 .Bl -tag -width indent
88 .It Va dev.cpu.%d.freq
89 Current active CPU frequency in MHz.
90 .It Va dev.cpu.%d.freq_driver
93 driver used by this cpu.
94 .It Va dev.cpu.%d.freq_levels
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/tremontx/
H A Duncore-other.json11 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
23 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
166 "ScaleUnit": "4Bytes",
182 "ScaleUnit": "4Bytes",
198 "ScaleUnit": "4Bytes",
214 "ScaleUnit": "4Bytes",
227 "ScaleUnit": "4Bytes",
240 "ScaleUnit": "4Bytes",
253 "ScaleUnit": "4Bytes",
266 "ScaleUnit": "4Bytes",
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2836.c63 #define BCM_LINTC_TIMER_CFG_REG(n) (0x40 + (n) * 4)
64 #define BCM_LINTC_MBOX_CFG_REG(n) (0x50 + (n) * 4)
65 #define BCM_LINTC_PENDING_REG(n) (0x60 + (n) * 4)
84 #define BCM_LINTC_PIRR_FIQ_EN_CORE(n) (1 << ((n) + 4))
88 #define BCM_LINTC_TCR_FIQ_EN_TIMER(n) (1 << ((n) + 4))
92 #define BCM_LINTC_MCR_FIQ_EN_MBOX(n) (1 << ((n) + 4))
98 #define BCM_LINTC_MBOX0_IRQ 4
165 #define BCM_LINTC_LOCK(sc) mtx_lock_spin(&(sc)->bls_mtx)
166 #define BCM_LINTC_UNLOCK(sc) mtx_unlock_spin(&(sc)->bls_mtx)
167 #define BCM_LINTC_LOCK_INIT(sc) mtx_init(&(sc)->bls_mtx, \
[all …]
/freebsd/sys/contrib/device-tree/src/arm/calxeda/
H A Dhighbank.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 cpu@900 {
22 compatible = "arm,cortex-a9";
[all …]
H A Decx-2000.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Diss4xx-mpic.dts15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Dcpu-topology.txt2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/freebsd/sys/dev/hwpmc/
H A Dhwpmc_cmn600.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2003-2008 Joseph Koshy
33 /* Arm CoreLink CMN-600 Coherent Mesh Network PMU Driver */
87 KASSERT(xpcntr < 4, ("[cmn600,%d] XP counter number %d is too big." in cmn600_pmu_readcntr()
94 if (width == 4) { in cmn600_pmu_readcntr()
112 KASSERT(xpcntr < 4, ("[cmn600,%d] XP counter number %d is too big." in cmn600_pmu_writecntr()
117 if (width == 4) { in cmn600_pmu_writecntr()
141 cmn600_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v) in cmn600_read_pmc() argument
147 KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), in cmn600_read_pmc()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/amazon/
H A Dalpine.dtsi27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
40 /* CPU Configuration */
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-sm
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/synaptics/
H A Das370.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-1.0";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu0: cpu@0 {
26 compatible = "arm,cortex-a53";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dsc9836.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #address-cells = <2>;
16 #size-cells = <0>;
18 cpu0: cpu@0 {
19 device_type = "cpu";
20 compatible = "arm,cortex-a53";
22 enable-method = "psci";
25 cpu1: cpu@1 {
26 device_type = "cpu";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Ds32v234.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2018 NXP
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
23 #address-cells = <2>;
24 #size-cells = <0>;
26 cpu0: cpu@0 {
[all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/cpu_model/
H A Dx86.c1 //===-- cpu_model/x86.c - Support for __cpu_model builtin --------*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
19 #error This file is intended only for x86-based targets
145 // has some not one-to-one mapped in llvm.
156 // a cpu string with no X86_FEATURE_COMPAT features, which is required in
264 /// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
290 int registers[4]; in getX86CpuIDAndInfo()
302 /// getX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return
[all …]
/freebsd/sys/amd64/include/
H A Dpcpu.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 char padding[128 - (2 * sizeof(int))];
53 * to each CPU's data can be set up for things like "check curproc on all
58 struct pcpu *pc_prvspace; /* Self-reference */ \
60 struct amd64tss *pc_tssp; /* TSS segment active on CPU */ \
69 u_int pc_acpi_id; /* ACPI CPU i
276 zpcpu_offset_cpu(cpu) global() argument
[all...]
/freebsd/sys/contrib/device-tree/src/arm/socionext/
H A Dmilbeaut-m10v.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DPPCTargetParser.def1 //===- PPCTargetParser.def - PPC target parsing defines ---------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
80 #define BUILTIN_PPC_UNSUPPORTED 4
97 PPC_CPU("ppc-cell-be",SYS_CALL,37,BUILTIN_PPC_FALSE,0)
114 PPC_LNX_FEATURE("4xxmac","4xx CPU has a Multiply Accumulator",PPCF_4XXMAC,0x02000000,PPC_FAWORD_HWC…
115 PPC_LNX_FEATURE("altivec","CPU has a SIMD/Vector Unit",PPCF_ALTIVEC,0x10000000,PPC_FAWORD_HWCAP)
116 PPC_LNX_FEATURE("arch_2_05","CPU supports ISA 205 (eg, POWER6)",PPCF_ARCH205,0x00001000,PPC_FAWORD_…
117 PPC_LNX_FEATURE("arch_2_06","CPU supports ISA 206 (eg, POWER7)",PPCF_ARCH206,0x00000100,PPC_FAWORD_…
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Drtsm_ve-aemv8a.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
38 #address-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/realtek/
H A Drtd16xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
32 no-map;
[all …]
H A Drtd1295.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
5 * Copyright (c) 2016-2019 Andreas Färber
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu0: cpu@0 {
18 device_type = "cpu";
19 compatible = "arm,cortex-a53";
21 next-level-cache = <&l2>;
24 cpu1: cpu@1 {
25 device_type = "cpu";
[all …]

12345678910>>...44