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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrFormats.td1 //===----------
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td1 //===- XtensaInstrFormats.td - Xtensa Instruction Formats --*- tablegen -*-===//
7 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
9 //===----------------------------------------------------------------------===//
32 field bits<24> Inst;
33 field bits<24> SoftFail = 0;
40 field bits<16> Inst;
41 field bits<16> SoftFail = 0;
45 class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
48 bits<4> r;
49 bits<4> s;
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrFormats.td1 //===-- MSP430InstrFormats.td - MSP430 Instruction Formats -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
13 class SourceMode<bits<2> val> {
14 bits<2> Value = val;
33 field bits<48> Inst;
34 field bits<48> SoftFail = 0;
46 class IForm<bits<4> opcode, DestMode ad, bit bw, SourceMode as, int size,
51 bits<4> rs;
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLSXInstrFormats.td1 // LoongArchLSXInstrFormats.td - LoongArch LSX Instr Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // vd/rd/cd - destination register operand.
14 // {r/v}{j/k} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
19 // 1RI13-type
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H A DLoongArchLASXInstrFormats.td1 // LoongArchLASXInstrFormats.td - LoongArch LASX Instr Formats - tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // xd/rd/cd - destination register operand.
14 // {r/x}{j/k} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
19 // 1RI13-type
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H A DLoongArchInstrFormats.td1 //===- LoongArchInstrFormats.td - LoongArch Instr. Formats -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // rd - destination register operand.
14 // r{j/k} - source register operand.
15 // immN - immediate data operand.
17 //===----------------------------------------------------------------------===//
22 field bits<32> Inst;
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H A DLoongArchLBTInstrFormats.td1 // LoongArchLBTInstrFormats.td - LoongArch LBT Instr Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
12 // opcode - operation code.
13 // rd/sd - destination register operand.
14 // rj/rk/sj - source register operand.
15 // immN/ptr - immediate data operand.
23 //===----------------------------------------------------------------------===//
25 // 1R-type (no outs)
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td1 //===- CSKYInstrFormats16Instr.td - 16-bit Instr. Formats -*- tablegen --*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 class J16<bits<5> sop, string opstr, dag ins>
12 bits<10> offset;
14 let Inst{14 - 10} = sop;
15 let Inst{9 - 0} = offset;
18 class J16_B<bits<5> sop, string opstr>
21 bits<10> offset;
23 let Inst{14 - 10} = sop;
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H A DCSKYInstrFormats.td1 //===-- CSKYInstrFormats.td - CSKY Instruction Formats -----*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 class AddrMode<bits<5> val> {
10 bits<5> Value = val;
14 def AddrMode32B : AddrMode<1>; // ld32.b, ld32.bs, st32.b, st32.bs, +4kb
17 def AddrMode16B : AddrMode<4>; // ld16.b, +32b
27 field bits<32> SoftFail = 0;
33 let TSFlags{4 - 0} = AM.Value;
42 class CSKY32Inst<AddrMode am, bits<6> opcode, dag outs, dag ins, string asmstr,
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H A DCSKYInstrFormatsF1.td1 //===- CSKYInstrFormatsF1.td - CSKY Float1.0 Instr Format --*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
17 class F_XYZ_BASE<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> patt…
19 bits<4> vrx;
20 bits<4> vry;
21 bits<4> vrz;
22 let Inst{25 - 21} = {0, vry};
23 let Inst{20 - 16} = {0, vrx};
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrFormats.td1 //===- MipsMSAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 let Inst{31-26} = 0b011110;
16 let Inst{31-26} = 0b010001;
20 let Inst{31-26} = 0b000000;
30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 bits<5> ws;
32 bits<5> wd;
33 bits<3> m;
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H A DMicroMipsInstrFormats.td1 //===-- MicroMipsInstrFormats.td - microMIPS Inst Formats -*- tablegen -*--===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
40 // Base class for MicroMIPS 16-bit instructions.
47 field bits<16> Inst;
48 field bits<16> SoftFail = 0;
49 bits<6> Opcode = 0x0;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrFormats.td1 //===-- ARMInstrFormats.td - ARM Instruction Formats -------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<6> val> {
18 bits<6> Value = val;
26 def DPFrm : Format<4>;
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrFormats.td1 //==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
27 // Some instructions come in pairs, one having a 12-bit displacement
28 // and the other having a 20-bit displacement. Both instructions in
34 // Many register-based <INSN>R instructions have a memory-based <INSN>
40 // MemKey identifies a targe reg-mem opcode, while MemType can be either
46 // Many distinct-operands instructions have older 2-operand equivalents.
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td1 //===-- RISCVInstrFormatsC.td - RISC-V C Instruction Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V C extension instruction formats.
11 //===----------------------------------------------------------------------===//
16 field bits<16> Inst;
21 field bits<16> SoftFail = 0;
25 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
28 bits<5> rs1;
29 bits<5> rs2;
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dxmmintrin.h1 /*===---- xmmintrin.h - SSE intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
36 __attribute__((__always_inline__, __nodebug__, __target__("sse,no-evex512"), \
40 __target__("mmx,sse,no-evex512"), __min_vector_width__(64)))
42 /// Adds the 32-bit float values in the low-order bits of the operands.
49 /// A 128-bit vector of [4 x float] containing one of the source operands.
50 /// The lower 32 bits of this operand are used in the calculation.
52 /// A 128-bit vector of [4 x float] containing one of the source operands.
53 /// The lower 32 bits of this operand are used in the calculation.
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H A Davxintrin.h1 /*===---- avxintrin.h - AVX intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
54 __attribute__((__always_inline__, __nodebug__, __target__("avx,no-evex512"), \
57 __attribute__((__always_inline__, __nodebug__, __target__("avx,no-evex512"), \
61 /// Adds two 256-bit vectors of [4 x double].
68 /// A 256-bit vector of [4 x double] containing one of the source operands.
70 /// A 256-bit vector of [4 x double] containing one of the source operands.
71 /// \returns A 256-bit vector of [4 x double] containing the sums of both
79 /// Adds two 256-bit vectors of [8 x float].
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td1 //===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 field bits<64> Inst;
15 field bits<64> SoftFail = 0;
21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> {
27 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
31 // e.g. s3 field may encode the signed integers values -1 .. 6
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/freebsd/sys/ofed/include/rdma/
H A Dib_smi.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
20 * - Redistributions of source code must retain the above
24 * - Redistributions in binary form must reproduce the above
100 u8 linkspeed_portstate; /* 4 bits, 4 bits */
101 u8 portphysstate_linkdown; /* 4 bits, 4 bits */
102 u8 mkeyprot_resv_lmc; /* 2 bits, 3, 3 */
103 u8 linkspeedactive_enabled; /* 4 bits, 4 bits */
104 u8 neighbormtu_mastersmsl; /* 4 bits, 4 bits */
105 u8 vlcap_inittype; /* 4 bits, 4 bits */
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrFormats.td1 //===-- XCoreInstrFormats.td - XCore Instruction Formats ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 field bits<32> Inst;
22 field bits<32> SoftFail = 0;
31 //===----------------------------------------------------------------------===//
33 //===----------------------------------------------------------------------===//
35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td1 //===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===//
5 // SPDX-Licens
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td1 //===-- AVRInstrInfo.td - AVR Instruction Formats -------
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/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_ia32cap.31 .\" -*- mode: troff; coding: utf-8 -*-
58 .TH OPENSSL_IA32CAP 3ossl 2025-09-30 3.5.4 OpenSSL
64 OPENSSL_ia32cap \- the x86[_64] processor capabilities vector
73 features. These extensions are denoted by individual bits or groups of bits
74 stored internally as ten 32\-bit capability vectors and for simplicity
75 represented logically below as five 64\-bit vectors. This logical
89 .SS "Notable Capability Bits for LV0"
90 .IX Subsection "Notable Capability Bits for LV0"
91 The following are notable capability bits from logical vector 0 (LV0)
94 .IP "bit #0+4 denoting presence of Time-Stamp Counter;" 4
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/freebsd/crypto/openssl/crypto/bn/asm/
H A Dvia-mont.pl2 # Copyright 2006-2020 The OpenSSL Project Authors. All Rights Reserved.
17 # Wrapper around 'rep montmul', VIA-specific instruction accessing
18 # PadLock Montgomery Multiplier. The wrapper is designed as drop-in
21 # Below are interleaved outputs from 'openssl speed rsa dsa' for 4
23 # Lines marked with "software integer" denote performance of hand-
24 # coded integer-only assembler found in OpenSSL 0.9.7. "Software SSE2"
25 # refers to hand-coded SSE2 Montgomery multiplication procedure found
32 # rsa 512 bits 0.001720s 0.000140s 581.4 7149.7 software integer
33 # rsa 512 bits 0.000690s 0.000086s 1450.3 11606.0 software SSE2
34 # rsa 512 bits 0.006136s 0.000201s 163.0 4974.5 hardware VIA SDK
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