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58 .TH OPENSSL_IA32CAP 3ossl 2025-09-30 3.5.4 OpenSSL
64 OPENSSL_ia32cap \- the x86[_64] processor capabilities vector
73 features. These extensions are denoted by individual bits or groups of bits
74 stored internally as ten 32\-bit capability vectors and for simplicity
75 represented logically below as five 64\-bit vectors. This logical
89 .SS "Notable Capability Bits for LV0"
90 .IX Subsection "Notable Capability Bits for LV0"
91 The following are notable capability bits from logical vector 0 (LV0)
94 .IP "bit #0+4 denoting presence of Time-Stamp Counter;" 4
95 .IX Item "bit #0+4 denoting presence of Time-Stamp Counter;"
97 .IP "bit #0+19 denoting availability of CLFLUSH instruction;" 4
99 .IP "bit #0+20, reserved by Intel, is used to choose among RC4 code paths;" 4
101 .IP "bit #0+23 denoting MMX support;" 4
103 .IP "bit #0+24, FXSR bit, denoting availability of XMM registers;" 4
105 .IP "bit #0+25 denoting SSE support;" 4
107 .IP "bit #0+26 denoting SSE2 support;" 4
109 .IP "bit #0+28 denoting Hyperthreading, which is used to distinguish cores with shared cache;" 4
111 .IP "bit #0+30, reserved by Intel, denotes specifically Intel CPUs;" 4
113 .IP "bit #0+33 denoting availability of PCLMULQDQ instruction;" 4
115 .IP "bit #0+41 denoting SSSE3, Supplemental SSE3, support;" 4
117 .IP "bit #0+43 denoting AMD XOP support (forced to zero on non-AMD CPUs);" 4
118 .IX Item "bit #0+43 denoting AMD XOP support (forced to zero on non-AMD CPUs);"
119 .IP "bit #0+54 denoting availability of MOVBE instruction;" 4
121 .IP "bit #0+57 denoting AES-NI instruction set extension;" 4
122 .IX Item "bit #0+57 denoting AES-NI instruction set extension;"
123 …58, XSAVE bit, lack of which in combination with MOVBE is used to identify Atom Silvermont core;" 4
125 .IP "bit #0+59, OSXSAVE bit, denoting availability of YMM registers;" 4
127 .IP "bit #0+60 denoting AVX extension;" 4
129 .IP "bit #0+62 denoting availability of RDRAND instruction;" 4
132 .SS "Notable Capability Bits for LV1"
133 .IX Subsection "Notable Capability Bits for LV1"
134 The following are notable capability bits from logical vector 1 (LV1)
137 .IP "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;" 4
140 .IP "bit #64+5 denoting availability of AVX2 instructions;" 4
142 .IP "bit #64+8 denoting availability of BMI2 instructions, e.g. MULX and RORX;" 4
144 .IP "bit #64+16 denoting availability of AVX512F extension;" 4
146 .IP "bit #64+17 denoting availability of AVX512DQ extension;" 4
148 .IP "bit #64+18 denoting availability of RDSEED instruction;" 4
150 .IP "bit #64+19 denoting availability of ADCX and ADOX instructions;" 4
152 .IP "bit #64+21 denoting availability of AVX512IFMA extension;" 4
154 .IP "bit #64+29 denoting availability of SHA extension;" 4
156 .IP "bit #64+30 denoting availability of AVX512BW extension;" 4
158 .IP "bit #64+31 denoting availability of AVX512VL extension;" 4
160 .IP "bit #64+41 denoting availability of VAES extension;" 4
162 .IP "bit #64+42 denoting availability of VPCLMULQDQ extension;" 4
165 .SS "Notable Capability Bits for LV2"
166 .IX Subsection "Notable Capability Bits for LV2"
167 The following are notable capability bits from logical vector 2 (LV2)
170 .IP "bit #128+15 denoting availability of Hybrid CPU;" 4
173 .IP "bit #128+29 denoting support for IA32_ARCH_CAPABILITIES MSR;" 4
175 .IP "bit #128+32 denoting availability of SHA512 extension;" 4
177 .IP "bit #128+33 denoting availability of SM3 extension;" 4
179 .IP "bit #128+34 denoting availability of SM4 extension;" 4
181 .IP "bit #128+55 denoting availability of AVX-IFMA extension;" 4
182 .IX Item "bit #128+55 denoting availability of AVX-IFMA extension;"
184 .SS "Notable Capability Bits for LV3"
185 .IX Subsection "Notable Capability Bits for LV3"
186 The following are notable capability bits from logical vector 3 (LV3)
189 .IP "bit #192+19 denoting availability of AVX10 Converged Vector ISA extension;" 4
192 .IP "bit #192+21 denoting availability of APX_F extension;" 4
195 .SS "Notable Capability Bits for LV4"
196 .IX Subsection "Notable Capability Bits for LV4"
197 The following are notable capability bits from logical vector 4 (LV4)
200 .IP "bits #256+32+[0:7] denoting AVX10 Converged Vector ISA Version (8 bits);" 4
201 .IX Item "bits #256+32+[0:7] denoting AVX10 Converged Vector ISA Version (8 bits);"
203 .IP "bit #256+48 denoting AVX10 XMM support;" 4
205 .IP "bit #256+49 denoting AVX10 YMM support;" 4
207 .IP "bit #256+50 denoting AVX10 ZMM support;" 4
214 The variable consists of a series of 64\-bit numbers representing each
220 Used in this form, each non-null logical vector will *overwrite* the entire corresponding
225 To illustrate, the following will zero all capability bits in logical vectors 1 and further
226 (disable all post-AVX extensions):
230 The following will zero all capability bits in logical vectors 2 and further:
234 The following will zero all capability bits only in logical vector 1:
252 Not all capability bits are copied from CPUID output verbatim. An example
256 the decision on whether or not expensive countermeasures against cache-timing attacks
263 Copyright 2004\-2021 The OpenSSL Project Authors. All Rights Reserved.