| /freebsd/contrib/googletest/googletest/test/ |
| H A D | googletest-listener-test.cc | 272 new EventRecordingListener2("3rd")); in main() 288 "3rd.OnTestProgramStart", in main() 291 "3rd.OnTestIterationStart(0)", in main() 294 "3rd.OnEnvironmentsSetUpStart", in main() 296 "3rd.OnEnvironmentsSetUpEnd", in main() 299 "3rd.OnTestSuiteStart", in main() 305 "3rd.OnTestStart", in main() 310 "3rd.OnTestPartResult", in main() 312 "3rd.OnTestEnd", in main() 317 "3rd.OnTestStart", in main() [all …]
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVCInstructions.h | 22 uint32_t rd; member 24 operator int() { return rd; } 25 operator Rd() { return Rd{rd + (shift ? 8 : 0)}; } in Rd() function 26 operator Rs() { return Rs{rd + (shift ? 8 : 0)}; } in Rs() 53 auto rd = DecodeCI_RD(inst); in DecodeC_LWSP() local 57 if (rd == 0) in DecodeC_LWSP() 59 return LW{rd, Rs{gpr_sp_riscv}, uint32_t(offset)}; in DecodeC_LWSP() 63 auto rd = DecodeCI_RD(inst); in DecodeC_LDSP() local 66 | ((inst >> 2) & 0x18); // offset[4:3] in DecodeC_LDSP() 67 if (rd == 0) in DecodeC_LDSP() [all …]
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| /freebsd/crypto/openssl/crypto/bn/asm/ |
| H A D | sparcv8.S | 63 rd %y,%g1 74 rd %y,%g1 85 rd %y,%g1 95 rd %y,%g1 117 rd %y,%g1 128 rd %y,%g1 140 rd %y,%g1 176 rd %y,%g1 183 rd %y,%g1 191 rd %y,%g1 [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.td | 103 def uimm3 : PatLeaf<(imm), [{ return isUInt<3>(N->getZExtValue()); }]>; 299 SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>, SDTCisVT<2, i64>]>; 301 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 303 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>, SDTCisVT<4, i64>]>; 314 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 397 def ICC_L : ICC_VAL< 3>; // Less 424 def CPCC_3 : CPCC_VAL<39>; // 3 426 def CPCC_23 : CPCC_VAL<37>; // 2 or 3 428 def CPCC_13 : CPCC_VAL<35>; // 1 or 3 430 def CPCC_123 : CPCC_VAL<33>; // 1 or 2 or 3 [all …]
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| H A D | SparcInstrAliases.td | 14 // mov<cond> <ccreg> rs2, rd 19 // mov<cond> (%icc|%xcc), rs2, rd 21 ", $rs2, $rd"), 22 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>; 24 // mov<cond> (%icc|%xcc), simm11, rd 26 ", $simm11, $rd"), 27 (movri IntRegs:$rd, i32imm:$simm11, condVal)>; 29 // fmovs<cond> (%icc|%xcc), $rs2, $rd 31 ", $rs2, $rd"), 32 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>; [all …]
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| /freebsd/sys/powerpc/powerpc/ |
| H A D | support.S | 62 #define LOG_WORD 3 194 #define rd %r4 macro 207 #define W4 3 215 dcbtst 0, rd 229 LOAD t4, WORD*3(rs) 231 STORE t1, 0(rd) 232 STORE t2, WORD*1(rd) 233 STORE t3, WORD*2(rd) 234 STORE t4, WORD*3(rd) 235 addi rd, rd, WORD*4 [all …]
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| /freebsd/usr.bin/gzip/ |
| H A D | unlz.c | 62 #define LITERAL_CONTEXT_BITS 3 77 #define LOW_BITS 3 78 #define MID_BITS 3 95 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 4, 5, 162 lz_rd_create(struct lz_range_decoder *rd, FILE *fp) in lz_rd_create() argument 164 rd->fp = fp; in lz_rd_create() 165 rd->code = 0; in lz_rd_create() 166 rd->range = ~0; in lz_rd_create() 168 rd->code = (rd->code << 8) | (uint8_t)getc(rd->fp); in lz_rd_create() 169 return ferror(rd->fp) ? -1 : 0; in lz_rd_create() [all …]
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| /freebsd/contrib/ldns/ |
| H A D | rdata.c | 24 ldns_rdf_size(const ldns_rdf *rd) in ldns_rdf_size() argument 26 assert(rd != NULL); in ldns_rdf_size() 27 return rd->_size; in ldns_rdf_size() 31 ldns_rdf_get_type(const ldns_rdf *rd) in ldns_rdf_get_type() argument 33 assert(rd != NULL); in ldns_rdf_get_type() 34 return rd->_type; in ldns_rdf_get_type() 38 ldns_rdf_data(const ldns_rdf *rd) in ldns_rdf_data() argument 40 assert(rd != NULL); in ldns_rdf_data() 41 return rd->_data; in ldns_rdf_data() 46 ldns_rdf_set_size(ldns_rdf *rd, size_t size) in ldns_rdf_set_size() argument [all …]
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| H A D | str2host.c | 37 ldns_str2rdf_int16(ldns_rdf **rd, const char *shortstr) in ldns_str2rdf_int16() argument 50 *rd = ldns_rdf_new_frm_data( in ldns_str2rdf_int16() 53 return *rd?LDNS_STATUS_OK:LDNS_STATUS_MEM_ERR; in ldns_str2rdf_int16() 58 ldns_str2rdf_time(ldns_rdf **rd, const char *time) in ldns_str2rdf_time() argument 102 *rd = ldns_rdf_new_frm_data( in ldns_str2rdf_time() 105 return *rd?LDNS_STATUS_OK:LDNS_STATUS_MEM_ERR; in ldns_str2rdf_time() 114 *rd = ldns_rdf_new_frm_data( in ldns_str2rdf_time() 117 return *rd?LDNS_STATUS_OK:LDNS_STATUS_MEM_ERR; in ldns_str2rdf_time() 127 ldns_str2rdf_nsec3_salt(ldns_rdf **rd, const char *salt_str) in ldns_str2rdf_nsec3_salt() argument 135 if(rd == NULL) { in ldns_str2rdf_nsec3_salt() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoC.td | 127 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 3>(Imm);}]> { 136 return isShiftedUInt<5, 3>(Imm); 158 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 3>(Imm);}]> { 167 return isShiftedUInt<6, 3>(Imm); 236 class CStackLoad<bits<3> funct3, string OpcodeStr, 238 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SPMem:$rs1, opnd:$imm), 239 OpcodeStr, "$rd, ${imm}(${rs1})">; 242 class CStackStore<bits<3> funct3, string OpcodeStr, 248 class CLoad_ri<bits<3> funct3, string OpcodeStr, 250 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRCMem:$rs1, opnd:$imm), [all …]
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| H A D | RISCVInstrInfoXqci.td | 31 [{return (Imm > 3) && isUInt<5>(Imm);}]> { 209 bits<3> func3; 212 bits<5> rd; 218 let Inst{11-7} = rd; 227 bits<3> func3; 230 bits<5> rd; 239 let Inst{11-7} = rd; 248 bits<3> func3; 261 let Inst{11-8} = imm12{3-0}; 271 bits<3> func3; [all …]
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| H A D | RISCVInstrFormatsC.td | 41 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 45 bits<5> rd; 49 let Inst{11-7} = rd; 57 class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 70 class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 74 bits<3> rd; 77 let Inst{4-2} = rd; 84 class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 87 bits<3> rd; 88 bits<3> rs1; [all …]
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| H A D | RISCVInstrInfoXSfmm.td | 39 bits<5> rd; 45 let Inst{11-7} = rd; 51 class SFInstTileMemOp<dag outs, dag ins, bits<3> nf, RISCVOpcode opcode, 71 class SFInstTileLoad<bits<3> nf, string opcodestr> 76 class SFInstTileStore<bits<3> nf, string opcodestr> 104 bits<4> rd; 111 let Inst{11-9} = rd{3-1}; 124 bits<4> rd; 132 let Inst{11-10} = rd{3-2}; 155 bits<4> rd; [all …]
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| H A D | RISCVInstrFormats.td | 36 def InstFormatI : InstFormat<3>; 64 class RISCVVConstraint<bits<3> val> { 65 bits<3> Value = val; 185 def EEWSEWx4 : EEW<3>; 202 bits<3> VLMul = 0; 246 // 3 -> widening case 300 : Pseudo<(outs GPR:$rd), (ins Ty:$rs1, Ty:$rs2), []> { 308 : Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> { 317 … : Pseudo<(outs GPR:$tmp, rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> { 340 class RVInstRBase<bits<3> funct3, RISCVOpcode opcode, dag outs, [all …]
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| H A D | RISCVInstrInfoXCV.td | 55 class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins, 65 class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr, 67 : CVInstBitManipRII<funct2, funct3, (outs GPR:$rd), 69 opcodestr, "$rd, $rs1, $is3, $is2">; 72 : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd), 73 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">; 76 : RVInstR<funct7, 0b011, OPC_CUSTOM_1, (outs GPR:$rd), 77 (ins GPR:$rs1), opcodestr, "$rd, $rs1"> { 82 class CVInstMac<bits<7> funct7, bits<3> funct3, string opcodestr> 84 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2), [all …]
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| H A D | RISCVInstrInfoXwch.td | 16 bits<3> rd_rs2; 64 def QK_C_LBU : RVInst16CL<0b001, 0b00, (outs GPRC:$rd), 66 "qk.c.lbu", "$rd, ${imm}(${rs1})">, 70 let Inst{11-10} = imm{4-3}; 81 let Inst{11-10} = imm{4-3}; 86 def QK_C_LHU : RVInst16CL<0b001, 0b10, (outs GPRC:$rd), 88 "qk.c.lhu", "$rd, ${imm}(${rs1})">, 91 let Inst{12-10} = imm{5-3}; 100 let Inst{12-10} = imm{5-3}; 128 let Inst{10-8} = imm{3-1}; [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchLBTInstrFormats.td | 13 // rd/sd - destination register operand. 41 bits<3> imm3; 63 // <opcode | I4 | rd> 65 : LAInst<(outs GPR:$rd), (ins uimm4:$imm4), 66 deriveInsnMnemonic<NAME>.ret, "$rd, $imm4"> { 68 bits<5> rd; 72 let Inst{4-0} = rd; 89 // <opcode | rd | I5 | I4> 100 let Inst{3-0} = imm4; 104 // <opcode | rd | I5 | I8> [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrInfo.td | 29 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 39 SDTCisVT<3, CondCodeVT>, // condition code 52 def SDT_ARMBr2JT : SDTypeProfile<0, 3, 59 SDTCisVT<3, i32>, SDTCisVT<4, i32>, 83 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, 88 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 89 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 93 def SDT_ARMMEMCPY : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 94 SDTCisVT<2, i32>, SDTCisVT<3, i32>, 111 SDTCisSameAs<0, 3>, [all …]
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| H A D | ARMInstrThumb2.td | 346 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 445 bits<4> Rd; 448 let Inst{11-8} = Rd; 458 bits<4> Rd; 462 let Inst{11-8} = Rd; 484 bits<4> Rd; 487 let Inst{11-8} = Rd; 488 let Inst{3-0} = ShiftedRm{3-0}; 497 bits<4> Rd; 500 let Inst{11-8} = Rd; [all …]
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| H A D | ARMInstrThumb.td | 337 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p), 1>; // A8.6.409 369 let Inst{3} = end; 379 bits<3> iflags; 382 let Inst{3} = 0; 393 bits<3> dst; 394 let Inst{6-3} = 0b1111; // Rm = pc 398 // ADD <Rd>, sp, #<imm8> 406 bits<3> dst; 459 let Inst{7} = Rdn{3}; 460 let Inst{6-3} = 0b1101; [all …]
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| /freebsd/sys/arm64/arm64/ |
| H A D | disassem.c | 47 #define OP_SF32 (1UL << 3) /* Force 32-bit access */ 49 #define OP_RD_SP (1UL << 7) /* Use sp for RD otherwise xzr */ 95 * OP <RD>, <RN>, <RM>{, <shift [LSL, LSR, ASR]> #imm} SF32/64 96 * OP <RD>, <RN>, #<imm>{, <shift [0, 12]>} SF32/64 97 * OP <RD>, <RM> {, <shift> #<imm> } 114 * OP <RD>, <RN|SP>, <RM> {, <extend> { #<amount> } } 160 { "add", "SF(1)|0001011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", 162 { "mov", "SF(1)|001000100000000000000|RN(5)|RD(5)", 164 { "add", "SF(1)|0010001|SHIFT(2)|IMM(12)|RN(5)|RD(5)", 168 { "adds", "SF(1)|0101011|SHIFT(2)|0|RM(5)|IMM(6)|RN(5)|RD(5)", [all …]
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| /freebsd/contrib/unbound/sldns/ |
| H A D | str2wire.c | 352 case LDNS_RDF_TYPE_WKS : /* it is the last rd field. */ in rrinternal_get_delims() 1117 if (key_len >= 4 && key_len <= 8 && !strncmp(key, "key", 3)) { in sldns_str2wire_svcparam_key_lookup() 1118 memcpy(buf, key + 3, key_len - 3); in sldns_str2wire_svcparam_key_lookup() 1119 buf[key_len - 3] = 0; in sldns_str2wire_svcparam_key_lookup() 1128 case 3: in sldns_str2wire_svcparam_key_lookup() 1175 sldns_str2wire_svcparam_port(const char* val, uint8_t* rd, size_t* rd_len) in sldns_str2wire_svcparam_port() argument 1189 sldns_write_uint16(rd, SVCB_KEY_PORT); in sldns_str2wire_svcparam_port() 1190 sldns_write_uint16(rd + 2, sizeof(uint16_t)); in sldns_str2wire_svcparam_port() 1191 sldns_write_uint16(rd + 4, port); in sldns_str2wire_svcparam_port() 1201 sldns_str2wire_svcbparam_ipv4hint(const char* val, uint8_t* rd, size_t* rd_len) in sldns_str2wire_svcbparam_ipv4hint() argument [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 33 def DestructiveBinaryImm : DestructiveInstTypeEnum<3>; 48 class SMEMatrixTypeEnum<bits<3> val> { 49 bits<3> Value = val; 54 def SMEMatrixTileS : SMEMatrixTypeEnum<3>; 86 let TSFlags{6-3} = DestructiveInstType.Value; 367 // Authenticated loads for v8.3 can have scaled 10-bit immediate offsets. 640 return CurDAG->getTargetConstant(N->getSExtValue() / 3, SDLoc(N), MVT::i64); 664 def SImm4s3Operand : SImmScaledMemoryIndexed<4, 3>; 683 [{ return Imm >=-24 && Imm <= 21 && (Imm % 3) == 0x0; }], SImmS3XForm> { 684 let PrintMethod = "printImmScale<3>"; [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrFormats.td | 57 bits<3> rd; 58 bits<3> rt; 59 bits<3> rs; 64 let Inst{9-7} = rd; 66 let Inst{3-1} = rs; 71 bits<3> rd; 72 bits<3> rs; 78 let Inst{9-7} = rd; 80 let Inst{3-0} = imm; 84 bits<3> rt; [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCDuplexInfo.cpp | 198 // Rd = memw(Rs+#u4:2) in getDuplexCandidateGroup() 199 // Rd = memub(Rs+#u4:0) in getDuplexCandidateGroup() 204 // Rd = memw(r29+#u5:2) in getDuplexCandidateGroup() 210 // Rd = memw(Rs+#u4:2) in getDuplexCandidateGroup() 218 // Rd = memub(Rs+#u4:0) in getDuplexCandidateGroup() 230 // Rd = memh/memuh(Rs+#u3:1) in getDuplexCandidateGroup() 231 // Rd = memb(Rs+#u3:0) in getDuplexCandidateGroup() 232 // Rd = memw(r29+#u5:2) - Handled above. in getDuplexCandidateGroup() 233 // Rdd = memd(r29+#u5:3) in getDuplexCandidateGroup() 239 // Rd = memh/memuh(Rs+#u3:1) in getDuplexCandidateGroup() [all …]
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