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/linux/sound/hda/codecs/
H A Dca0132_regs.h33 #define XRAM_XRAM_INST_OFFSET(_chan) \ argument
35 (_chan * XRAM_XRAM_CHAN_INCR))
41 #define YRAM_YRAM_INST_OFFSET(_chan) \ argument
43 (_chan * YRAM_YRAM_CHAN_INCR))
49 #define UC_UC_INST_OFFSET(_chan) \ argument
51 (_chan * UC_UC_CHAN_INCR))
57 #define AXRAM_AXRAM_INST_OFFSET(_chan) \ argument
59 (_chan * AXRAM_AXRAM_CHAN_INCR))
65 #define AYRAM_AYRAM_INST_OFFSET(_chan) \ argument
67 (_chan * AYRAM_AYRAM_CHAN_INCR))
[all …]
/linux/drivers/iio/adc/
H A Dltc2497-core.c20 #define LTC2497_SIGN BIT(3)
108 #define LTC2497_CHAN(_chan, _addr, _ds_name) { \ argument
111 .channel = (_chan), \
112 .address = (_addr | (_chan / 2) | ((_chan & 1) ? LTC2497_SIGN : 0)), \
118 #define LTC2497_CHAN_DIFF(_chan, _addr) { \ argument
121 .channel = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 1 : 0), \
122 .channel2 = (_chan) * 2 + ((_addr) & LTC2497_SIGN ? 0 : 1),\
123 .address = (_addr | _chan), \
133 LTC2497_CHAN(3, LTC2497_SGL, "CH3"),
149 LTC2497_CHAN_DIFF(3, LTC2497_DIFF),
[all …]
H A Dad7266.c32 struct spi_transfer single_xfer[3];
38 struct gpio_desc *gpios[3];
117 for (i = 0; i < 3; ++i) in ad7266_select_input()
189 #define AD7266_CHAN(_chan, _sign) { \ argument
192 .channel = (_chan), \
193 .address = (_chan), \
197 .scan_index = (_chan), \
212 AD7266_CHAN(3, (_sign)), \
236 #define AD7266_CHAN_DIFF(_chan, _sign) { \ argument
239 .channel = (_chan) * 2, \
[all …]
H A Dltc2309.c26 #define LTC2309_DIN_UNI BIT(3)
63 #define LTC2309_CHAN(_chan, _addr) { \ argument
67 .channel = _chan, \
72 #define LTC2309_DIFF_CHAN(_chan, _chan2, _addr) { \ argument
77 .channel = _chan, \
87 LTC2309_CHAN(3, LTC2309_CH3),
93 LTC2309_DIFF_CHAN(2, 3, LTC2309_CH2_CH3),
97 LTC2309_DIFF_CHAN(3, 2, LTC2309_CH3_CH2),
H A Dxilinx-xadc-core.c380 if (div <= 3) in xadc_zynq_setup()
526 events |= (status & 0x0001) << 3; in xadc_axi_interrupt_handler()
547 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) | in xadc_axi_update_alarm()
1056 #define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \ argument
1059 .channel = (_chan), \
1077 #define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \ argument
1080 .channel = (_chan), \
1099 #define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \ argument
1100 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
1101 #define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \ argument
[all …]
H A Dad7292.c45 #define AD7292_VOLTAGE_CHAN(_chan) \ argument
51 .channel = _chan, \
58 AD7292_VOLTAGE_CHAN(3),
75 AD7292_VOLTAGE_CHAN(3),
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp.h39 * | port 0 | port 1 | port 2 | port 3 | port 4 | port 5 | port 6 | port 7 |
50 * ||port 0|port 1|port 2|port 3|||port 0|port 1|port 2|port 3||
194 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8)) argument
195 #define GLTSYN_AUX_IN(_chan, _idx) (GLTSYN_AUX_IN_0(_idx) + ((_chan) * 8)) argument
196 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8)) argument
197 #define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16)) argument
198 #define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16)) argument
199 #define GLTSYN_EVNT_L(_chan, _idx) (GLTSYN_EVNT_L_0(_idx) + ((_chan) * 16)) argument
200 #define GLTSYN_EVNT_H(_chan, _idx) (GLTSYN_EVNT_H_0(_idx) + ((_chan) * 16)) argument
201 #define GLTSYN_EVNT_H_IDX_MAX 3
/linux/drivers/iio/dac/
H A Drohm-bd79703.c87 #define BD79703_CHAN_ADDR(_chan, _addr) { \ argument
91 .channel = (_chan), \
97 #define BD79703_CHAN(_chan) BD79703_CHAN_ADDR((_chan), (_chan) + 1) argument
112 * and 3, but to the channels 0, 1, 4, 5. So the addressing used with SPI
120 BD79703_CHAN_ADDR(3, 6),
127 BD79703_CHAN(3),
H A Dad5624r_spi.c29 u8 msg[3]; in ad5624r_spi_write()
34 * followed by the 3-bit DAC address, A2 to A0, and then the in ad5624r_spi_write()
166 #define AD5624R_CHANNEL(_chan, _bits) { \ argument
170 .channel = (_chan), \
173 .address = (_chan), \
188 AD5624R_CHANNEL(3, _bits), \
H A Dad5504.c248 #define AD5504_CHANNEL(_chan) { \ argument
252 .channel = (_chan), \
255 .address = AD5504_ADDR_DAC(_chan), \
268 AD5504_CHANNEL(3),
H A Dad5766.c32 #define AD5766_CMD_WR_IN_REG(x) (0x10 | ((x) & GENMASK(3, 0)))
33 #define AD5766_CMD_WR_DAC_REG(x) (0x20 | ((x) & GENMASK(3, 0)))
39 #define AD5766_CMD_READBACK_REG(x) (0x80 | ((x) & GENMASK(3, 0)))
109 * 3: 0.25 SCALING.
126 } data[3] __aligned(IIO_DMA_MINALIGN);
151 .len = 3, in __ad5766_spi_read()
156 .len = 3, in __ad5766_spi_read()
177 return spi_write(st->spi, &st->data[0].b8[0], 3); in __ad5766_spi_write()
441 #define AD576x_CHANNEL(_chan, _bits) { \ argument
445 .channel = (_chan), \
[all …]
H A Dltc2632.c76 u8 msg[3]; in ltc2632_spi_write()
182 #define LTC2632_CHANNEL(_chan, _bits) { \ argument
186 .channel = (_chan), \
189 .address = (_chan), \
202 LTC2632_CHANNEL(3, _bits), \
H A Dad3530r.c282 #define AD3530R_CHAN(_chan) \ argument
286 .channel = _chan, \
297 AD3530R_CHAN(3),
308 AD3530R_CHAN(3),
398 FIELD_PREP(AD3530R_OP_MODE_CHAN_MSK(3), AD3530R_NORMAL_OP); in ad3530r_setup()
H A Dltc2688.c45 #define LTC2688_CH_OVERRANGE_MSK BIT(3)
47 #define LTC2688_CH_TGP_MAX 3
97 u8 rx_data[3];
110 .tx_buf = st->tx_data + 3, in ltc2688_spi_read()
659 #define LTC2688_CHANNEL(_chan) { \ argument
663 .channel = (_chan), \
675 LTC2688_CHANNEL(3),
955 st->tx_data[3] = LTC2688_CMD_NOOP; in ltc2688_probe()
/linux/drivers/dma/
H A Dfsl-edma-common.h15 #define EDMA_CR_ERGA BIT(3)
29 #define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
40 #define EDMA_TCD_CSR_D_REQ BIT(3)
77 #define EDMA_V3_CH_ERR_NCE BIT(3)
210 #define FSL_EDMA_DRV_WRAP_IO BIT(3)
332 #define fsl_edma_get_tcd(_chan, _tcd, _field) \ argument
333 (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? (((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \
343 #define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field) \ argument
344 (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? \
355 #define fsl_edma_set_tcd_to_le(_chan, _tcd, _val, _field) \ argument
[all …]
H A Dfsl-edma-main.c255 struct dma_chan *chan, *_chan; in fsl_edma_xlate() local
265 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { in fsl_edma_xlate()
298 struct dma_chan *chan, *_chan; in fsl_edma3_xlate() local
303 if (dma_spec->args_count != 3) in fsl_edma3_xlate()
309 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, in fsl_edma3_xlate()
H A Dat_xdmac.c66 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
74 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
82 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
90 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
107 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
173 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
424 struct dma_chan *chan, *_chan; in at_xdmac_off() local
[all …]
H A Dfsl-edma-common.c188 int endian_diff[4] = {3, 1, -1, -3}; in fsl_edma_chan_mux()
892 struct fsl_edma_chan *chan, *_chan; in fsl_edma_cleanup_vchan() local
894 list_for_each_entry_safe(chan, _chan, in fsl_edma_cleanup_vchan()
H A Dfsl-qdma.c371 csgf_dest = fsl_comp->virt_addr + 3; in fsl_qdma_comp_fill_memcpy()
1262 struct fsl_qdma_chan *chan, *_chan; in fsl_qdma_cleanup_vchan() local
1264 list_for_each_entry_safe(chan, _chan, in fsl_qdma_cleanup_vchan()
H A Dmv_xor.c547 win_enable |= 3 << (16 + (2 * i)); in mv_xor_add_io_win()
1011 struct dma_chan *chan, *_chan; in mv_xor_channel_remove() local
1023 list_for_each_entry_safe(chan, _chan, &mv_chan->dmadev.channels, in mv_xor_channel_remove()
1206 win_enable |= 3 << (16 + (2 * i)); in mv_xor_conf_mbus_windows()
1234 win_enable |= 3 << 16; in mv_xor_conf_mbus_windows_a3700()
/linux/drivers/input/touchscreen/
H A Dtsc2007_iio.c15 #define TSC2007_CHAN_IIO(_chan, _name, _type, _chan_info) \ argument
22 .channel = _chan, \
29 TSC2007_CHAN_IIO(3, "z2", IIO_VOLTAGE, IIO_CHAN_INFO_RAW),
64 case 3: in tsc2007_read_raw()
/linux/drivers/iio/cdc/
H A Dad7150.c25 #define AD7150_STATUS_OUT1 BIT(3)
28 #define AD7150_CH2_DATA_HIGH_REG 3
34 #define AD7150_CH_TIMEOUT_RECEDING GENMASK(3, 0)
71 * 3:0 are for timeout receding - applies if below lower threshold
201 ad7150_addresses[chan][3], in ad7150_write_event_params()
437 #define AD7150_CAPACITANCE_CHAN(_chan) { \ argument
440 .channel = _chan, \
450 #define AD7150_CAPACITANCE_CHAN_NO_IRQ(_chan) { \ argument
453 .channel = _chan, \
/linux/drivers/comedi/drivers/
H A Ddas6402.c45 #define DAS6402_STATUS_XINT BIT(3)
62 #define DAS6402_CTRL_PACER_TRIG DAS6402_CTRL_TRIG(3)
64 #define DAS6402_CTRL_XINTE BIT(3)
71 #define DAS6402_TRIG_PRETRIG BIT(3)
72 #define DAS6402_AO_RANGE(_chan, _range) ((_range) << ((_chan) ? 6 : 4)) argument
73 #define DAS6402_AO_RANGE_MASK(_chan) (3 << ((_chan) ? 6 : 4)) argument
79 #define DAS6402_MODE_EOB DAS6402_MODE_RANGE(3)
314 /* Step 3: check if arguments are trivially valid */ in das6402_ai_cmdtest()
329 return 3; in das6402_ai_cmdtest()
569 /* IRQs 2,3,5,6,7, 10,11,15 are valid for "enhanced" mode */ in das6402_attach()
[all …]
/linux/Documentation/devicetree/bindings/dma/ti/
H A Dk3-pktdma.yaml189 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
190 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
/linux/drivers/regulator/
H A Dmax5970-regulator.c45 *val = (reg_data[0] << 2) | (reg_data[1] & 3); in max5970_read_adc()
366 #define MAX597X_SWITCH(_ID, _ereg, _chan, _supply) { \ argument
376 .enable_mask = CHXEN((_chan)), \

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