xref: /linux/drivers/iio/adc/ti-ads7924.c (revision a1ff5a7d78a036d6c2178ee5acd6ba4946243800)
14d82b2f9SHugo Villeneuve // SPDX-License-Identifier: GPL-2.0
24d82b2f9SHugo Villeneuve /*
34d82b2f9SHugo Villeneuve  * IIO driver for Texas Instruments ADS7924 ADC, 12-bit, 4-Channels, I2C
44d82b2f9SHugo Villeneuve  *
54d82b2f9SHugo Villeneuve  * Author: Hugo Villeneuve <hvilleneuve@dimonoff.com>
64d82b2f9SHugo Villeneuve  * Copyright 2022 DimOnOff
74d82b2f9SHugo Villeneuve  *
84d82b2f9SHugo Villeneuve  * based on iio/adc/ti-ads1015.c
94d82b2f9SHugo Villeneuve  * Copyright (c) 2016, Intel Corporation.
104d82b2f9SHugo Villeneuve  *
114d82b2f9SHugo Villeneuve  * Datasheet: https://www.ti.com/lit/gpn/ads7924
124d82b2f9SHugo Villeneuve  */
134d82b2f9SHugo Villeneuve 
144d82b2f9SHugo Villeneuve #include <linux/bitfield.h>
154d82b2f9SHugo Villeneuve #include <linux/delay.h>
164d82b2f9SHugo Villeneuve #include <linux/gpio/consumer.h>
174d82b2f9SHugo Villeneuve #include <linux/init.h>
184d82b2f9SHugo Villeneuve #include <linux/irq.h>
194d82b2f9SHugo Villeneuve #include <linux/i2c.h>
204d82b2f9SHugo Villeneuve #include <linux/module.h>
214d82b2f9SHugo Villeneuve #include <linux/mutex.h>
224d82b2f9SHugo Villeneuve #include <linux/regmap.h>
234d82b2f9SHugo Villeneuve #include <linux/regulator/consumer.h>
244d82b2f9SHugo Villeneuve 
254d82b2f9SHugo Villeneuve #include <linux/iio/iio.h>
264d82b2f9SHugo Villeneuve #include <linux/iio/types.h>
274d82b2f9SHugo Villeneuve 
284d82b2f9SHugo Villeneuve #define ADS7924_CHANNELS	 4
294d82b2f9SHugo Villeneuve #define ADS7924_BITS		12
304d82b2f9SHugo Villeneuve #define ADS7924_DATA_SHIFT	 4
314d82b2f9SHugo Villeneuve 
324d82b2f9SHugo Villeneuve /* Registers. */
334d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_REG	0x00
344d82b2f9SHugo Villeneuve #define ADS7924_INTCNTRL_REG	0x01
354d82b2f9SHugo Villeneuve #define ADS7924_DATA0_U_REG	0x02
364d82b2f9SHugo Villeneuve #define ADS7924_DATA0_L_REG	0x03
374d82b2f9SHugo Villeneuve #define ADS7924_DATA1_U_REG	0x04
384d82b2f9SHugo Villeneuve #define ADS7924_DATA1_L_REG	0x05
394d82b2f9SHugo Villeneuve #define ADS7924_DATA2_U_REG	0x06
404d82b2f9SHugo Villeneuve #define ADS7924_DATA2_L_REG	0x07
414d82b2f9SHugo Villeneuve #define ADS7924_DATA3_U_REG	0x08
424d82b2f9SHugo Villeneuve #define ADS7924_DATA3_L_REG	0x09
434d82b2f9SHugo Villeneuve #define ADS7924_ULR0_REG	0x0A
444d82b2f9SHugo Villeneuve #define ADS7924_LLR0_REG	0x0B
454d82b2f9SHugo Villeneuve #define ADS7924_ULR1_REG	0x0C
464d82b2f9SHugo Villeneuve #define ADS7924_LLR1_REG	0x0D
474d82b2f9SHugo Villeneuve #define ADS7924_ULR2_REG	0x0E
484d82b2f9SHugo Villeneuve #define ADS7924_LLR2_REG	0x0F
494d82b2f9SHugo Villeneuve #define ADS7924_ULR3_REG	0x10
504d82b2f9SHugo Villeneuve #define ADS7924_LLR3_REG	0x11
514d82b2f9SHugo Villeneuve #define ADS7924_INTCONFIG_REG	0x12
524d82b2f9SHugo Villeneuve #define ADS7924_SLPCONFIG_REG	0x13
534d82b2f9SHugo Villeneuve #define ADS7924_ACQCONFIG_REG	0x14
544d82b2f9SHugo Villeneuve #define ADS7924_PWRCONFIG_REG	0x15
554d82b2f9SHugo Villeneuve #define ADS7924_RESET_REG	0x16
564d82b2f9SHugo Villeneuve 
574d82b2f9SHugo Villeneuve /*
584d82b2f9SHugo Villeneuve  * Register address INC bit: when set to '1', the register address is
594d82b2f9SHugo Villeneuve  * automatically incremented after every register read which allows convenient
604d82b2f9SHugo Villeneuve  * reading of multiple registers. Set INC to '0' when reading a single register.
614d82b2f9SHugo Villeneuve  */
624d82b2f9SHugo Villeneuve #define ADS7924_AUTO_INCREMENT_BIT	BIT(7)
634d82b2f9SHugo Villeneuve 
644d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_MODE_MASK	GENMASK(7, 2)
654d82b2f9SHugo Villeneuve 
664d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_SEL_MASK	GENMASK(1, 0)
674d82b2f9SHugo Villeneuve 
684d82b2f9SHugo Villeneuve #define ADS7924_CFG_INTPOL_BIT		1
694d82b2f9SHugo Villeneuve #define ADS7924_CFG_INTTRIG_BIT		0
704d82b2f9SHugo Villeneuve 
714d82b2f9SHugo Villeneuve #define ADS7924_CFG_INTPOL_MASK		BIT(ADS7924_CFG_INTPOL_BIT)
724d82b2f9SHugo Villeneuve #define ADS7924_CFG_INTTRIG_MASK	BIT(ADS7924_CFG_INTTRIG_BIT)
734d82b2f9SHugo Villeneuve 
744d82b2f9SHugo Villeneuve /* Interrupt pin polarity */
754d82b2f9SHugo Villeneuve #define ADS7924_CFG_INTPOL_LOW		0
764d82b2f9SHugo Villeneuve #define ADS7924_CFG_INTPOL_HIGH		1
774d82b2f9SHugo Villeneuve 
784d82b2f9SHugo Villeneuve /* Interrupt pin signaling */
794d82b2f9SHugo Villeneuve #define ADS7924_CFG_INTTRIG_LEVEL	0
804d82b2f9SHugo Villeneuve #define ADS7924_CFG_INTTRIG_EDGE	1
814d82b2f9SHugo Villeneuve 
824d82b2f9SHugo Villeneuve /* Mode control values */
834d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_IDLE			0x00
844d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_AWAKE			0x20
854d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_MANUAL_SINGLE		0x30
864d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_MANUAL_SCAN		0x32
874d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_AUTO_SINGLE		0x31
884d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_AUTO_SCAN		0x33
894d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_AUTO_SINGLE_SLEEP	0x39
904d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_AUTO_SCAN_SLEEP	0x3B
914d82b2f9SHugo Villeneuve #define ADS7924_MODECNTRL_AUTO_BURST_SLEEP	0x3F
924d82b2f9SHugo Villeneuve 
934d82b2f9SHugo Villeneuve #define ADS7924_ACQTIME_MASK	GENMASK(4, 0)
944d82b2f9SHugo Villeneuve 
954d82b2f9SHugo Villeneuve #define ADS7924_PWRUPTIME_MASK	GENMASK(4, 0)
964d82b2f9SHugo Villeneuve 
974d82b2f9SHugo Villeneuve /*
984d82b2f9SHugo Villeneuve  * The power-up time is allowed to elapse whenever the device has been shutdown
994d82b2f9SHugo Villeneuve  * in idle mode. Power-up time can allow external circuits, such as an
1004d82b2f9SHugo Villeneuve  * operational amplifier, between the MUXOUT and ADCIN pins to turn on.
1014d82b2f9SHugo Villeneuve  * The nominal time programmed by the PUTIME[4:0] register bits is given by:
1024d82b2f9SHugo Villeneuve  *     t PU = PWRUPTIME[4:0] × 2 μs
1034d82b2f9SHugo Villeneuve  * If a power-up time is not required, set the bits to '0' to effectively bypass.
1044d82b2f9SHugo Villeneuve  */
1054d82b2f9SHugo Villeneuve #define ADS7924_PWRUPTIME_US 0 /* Bypass (0us). */
1064d82b2f9SHugo Villeneuve 
1074d82b2f9SHugo Villeneuve /*
1084d82b2f9SHugo Villeneuve  * Acquisition Time according to ACQTIME[4:0] register bits.
1094d82b2f9SHugo Villeneuve  * The Acquisition Time is given by:
1104d82b2f9SHugo Villeneuve  *     t ACQ = (ACQTIME[4:0] × 2 μs) + 6 μs
1114d82b2f9SHugo Villeneuve  * Using default value of 0 for ACQTIME[4:0] results in a minimum acquisition
1124d82b2f9SHugo Villeneuve  * time of 6us.
1134d82b2f9SHugo Villeneuve  */
1144d82b2f9SHugo Villeneuve #define ADS7924_ACQTIME_US 6
1154d82b2f9SHugo Villeneuve 
1164d82b2f9SHugo Villeneuve /* The conversion time is always 4μs and cannot be programmed by the user. */
1174d82b2f9SHugo Villeneuve #define ADS7924_CONVTIME_US 4
1184d82b2f9SHugo Villeneuve 
1194d82b2f9SHugo Villeneuve #define ADS7924_TOTAL_CONVTIME_US (ADS7924_PWRUPTIME_US + ADS7924_ACQTIME_US + \
1204d82b2f9SHugo Villeneuve 				   ADS7924_CONVTIME_US)
1214d82b2f9SHugo Villeneuve 
1224d82b2f9SHugo Villeneuve #define ADS7924_V_CHAN(_chan, _addr) {				\
1234d82b2f9SHugo Villeneuve 	.type = IIO_VOLTAGE,					\
1244d82b2f9SHugo Villeneuve 	.indexed = 1,						\
1254d82b2f9SHugo Villeneuve 	.channel = _chan,					\
1264d82b2f9SHugo Villeneuve 	.address = _addr,					\
1274d82b2f9SHugo Villeneuve 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 		\
1284d82b2f9SHugo Villeneuve 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
1294d82b2f9SHugo Villeneuve 	.datasheet_name = "AIN"#_chan,				\
1304d82b2f9SHugo Villeneuve }
1314d82b2f9SHugo Villeneuve 
1324d82b2f9SHugo Villeneuve struct ads7924_data {
1334d82b2f9SHugo Villeneuve 	struct device *dev;
1344d82b2f9SHugo Villeneuve 	struct regmap *regmap;
1354d82b2f9SHugo Villeneuve 	struct regulator *vref_reg;
1364d82b2f9SHugo Villeneuve 
1374d82b2f9SHugo Villeneuve 	/* GPIO descriptor for device hard-reset pin. */
1384d82b2f9SHugo Villeneuve 	struct gpio_desc *reset_gpio;
1394d82b2f9SHugo Villeneuve 
1404d82b2f9SHugo Villeneuve 	/*
1414d82b2f9SHugo Villeneuve 	 * Protects ADC ops, e.g: concurrent sysfs/buffered
1424d82b2f9SHugo Villeneuve 	 * data reads, configuration updates
1434d82b2f9SHugo Villeneuve 	 */
1444d82b2f9SHugo Villeneuve 	struct mutex lock;
1454d82b2f9SHugo Villeneuve 
1464d82b2f9SHugo Villeneuve 	/*
1474d82b2f9SHugo Villeneuve 	 * Set to true when the ADC is switched to the continuous-conversion
1484d82b2f9SHugo Villeneuve 	 * mode and exits from a power-down state. This flag is used to avoid
1494d82b2f9SHugo Villeneuve 	 * getting the stale result from the conversion register.
1504d82b2f9SHugo Villeneuve 	 */
1514d82b2f9SHugo Villeneuve 	bool conv_invalid;
1524d82b2f9SHugo Villeneuve };
1534d82b2f9SHugo Villeneuve 
ads7924_is_writeable_reg(struct device * dev,unsigned int reg)1544d82b2f9SHugo Villeneuve static bool ads7924_is_writeable_reg(struct device *dev, unsigned int reg)
1554d82b2f9SHugo Villeneuve {
1564d82b2f9SHugo Villeneuve 	switch (reg) {
1574d82b2f9SHugo Villeneuve 	case ADS7924_MODECNTRL_REG:
1584d82b2f9SHugo Villeneuve 	case ADS7924_INTCNTRL_REG:
1594d82b2f9SHugo Villeneuve 	case ADS7924_ULR0_REG:
1604d82b2f9SHugo Villeneuve 	case ADS7924_LLR0_REG:
1614d82b2f9SHugo Villeneuve 	case ADS7924_ULR1_REG:
1624d82b2f9SHugo Villeneuve 	case ADS7924_LLR1_REG:
1634d82b2f9SHugo Villeneuve 	case ADS7924_ULR2_REG:
1644d82b2f9SHugo Villeneuve 	case ADS7924_LLR2_REG:
1654d82b2f9SHugo Villeneuve 	case ADS7924_ULR3_REG:
1664d82b2f9SHugo Villeneuve 	case ADS7924_LLR3_REG:
1674d82b2f9SHugo Villeneuve 	case ADS7924_INTCONFIG_REG:
1684d82b2f9SHugo Villeneuve 	case ADS7924_SLPCONFIG_REG:
1694d82b2f9SHugo Villeneuve 	case ADS7924_ACQCONFIG_REG:
1704d82b2f9SHugo Villeneuve 	case ADS7924_PWRCONFIG_REG:
1714d82b2f9SHugo Villeneuve 	case ADS7924_RESET_REG:
1724d82b2f9SHugo Villeneuve 		return true;
1734d82b2f9SHugo Villeneuve 	default:
1744d82b2f9SHugo Villeneuve 		return false;
1754d82b2f9SHugo Villeneuve 	}
1764d82b2f9SHugo Villeneuve }
1774d82b2f9SHugo Villeneuve 
1784d82b2f9SHugo Villeneuve static const struct regmap_config ads7924_regmap_config = {
1794d82b2f9SHugo Villeneuve 	.reg_bits = 8,
1804d82b2f9SHugo Villeneuve 	.val_bits = 8,
1814d82b2f9SHugo Villeneuve 	.max_register = ADS7924_RESET_REG,
1824d82b2f9SHugo Villeneuve 	.writeable_reg = ads7924_is_writeable_reg,
1834d82b2f9SHugo Villeneuve };
1844d82b2f9SHugo Villeneuve 
1854d82b2f9SHugo Villeneuve static const struct iio_chan_spec ads7924_channels[] = {
1864d82b2f9SHugo Villeneuve 	ADS7924_V_CHAN(0, ADS7924_DATA0_U_REG),
1874d82b2f9SHugo Villeneuve 	ADS7924_V_CHAN(1, ADS7924_DATA1_U_REG),
1884d82b2f9SHugo Villeneuve 	ADS7924_V_CHAN(2, ADS7924_DATA2_U_REG),
1894d82b2f9SHugo Villeneuve 	ADS7924_V_CHAN(3, ADS7924_DATA3_U_REG),
1904d82b2f9SHugo Villeneuve };
1914d82b2f9SHugo Villeneuve 
ads7924_get_adc_result(struct ads7924_data * data,struct iio_chan_spec const * chan,int * val)1924d82b2f9SHugo Villeneuve static int ads7924_get_adc_result(struct ads7924_data *data,
1934d82b2f9SHugo Villeneuve 				  struct iio_chan_spec const *chan, int *val)
1944d82b2f9SHugo Villeneuve {
1954d82b2f9SHugo Villeneuve 	int ret;
1964d82b2f9SHugo Villeneuve 	__be16 be_val;
1974d82b2f9SHugo Villeneuve 
1984d82b2f9SHugo Villeneuve 	if (chan->channel < 0 || chan->channel >= ADS7924_CHANNELS)
1994d82b2f9SHugo Villeneuve 		return -EINVAL;
2004d82b2f9SHugo Villeneuve 
2014d82b2f9SHugo Villeneuve 	if (data->conv_invalid) {
2024d82b2f9SHugo Villeneuve 		int conv_time;
2034d82b2f9SHugo Villeneuve 
2044d82b2f9SHugo Villeneuve 		conv_time = ADS7924_TOTAL_CONVTIME_US;
2054d82b2f9SHugo Villeneuve 		/* Allow 10% for internal clock inaccuracy. */
2064d82b2f9SHugo Villeneuve 		conv_time += conv_time / 10;
2074d82b2f9SHugo Villeneuve 		usleep_range(conv_time, conv_time + 1);
2084d82b2f9SHugo Villeneuve 		data->conv_invalid = false;
2094d82b2f9SHugo Villeneuve 	}
2104d82b2f9SHugo Villeneuve 
2114d82b2f9SHugo Villeneuve 	ret = regmap_raw_read(data->regmap, ADS7924_AUTO_INCREMENT_BIT |
2124d82b2f9SHugo Villeneuve 			      chan->address, &be_val, sizeof(be_val));
2134d82b2f9SHugo Villeneuve 	if (ret)
2144d82b2f9SHugo Villeneuve 		return ret;
2154d82b2f9SHugo Villeneuve 
2164d82b2f9SHugo Villeneuve 	*val = be16_to_cpu(be_val) >> ADS7924_DATA_SHIFT;
2174d82b2f9SHugo Villeneuve 
2184d82b2f9SHugo Villeneuve 	return 0;
2194d82b2f9SHugo Villeneuve }
2204d82b2f9SHugo Villeneuve 
ads7924_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)2214d82b2f9SHugo Villeneuve static int ads7924_read_raw(struct iio_dev *indio_dev,
2224d82b2f9SHugo Villeneuve 			    struct iio_chan_spec const *chan, int *val,
2234d82b2f9SHugo Villeneuve 			    int *val2, long mask)
2244d82b2f9SHugo Villeneuve {
2254d82b2f9SHugo Villeneuve 	int ret, vref_uv;
2264d82b2f9SHugo Villeneuve 	struct ads7924_data *data = iio_priv(indio_dev);
2274d82b2f9SHugo Villeneuve 
2284d82b2f9SHugo Villeneuve 	switch (mask) {
2294d82b2f9SHugo Villeneuve 	case IIO_CHAN_INFO_RAW:
2304d82b2f9SHugo Villeneuve 		mutex_lock(&data->lock);
2314d82b2f9SHugo Villeneuve 		ret = ads7924_get_adc_result(data, chan, val);
2324d82b2f9SHugo Villeneuve 		mutex_unlock(&data->lock);
2334d82b2f9SHugo Villeneuve 		if (ret < 0)
2344d82b2f9SHugo Villeneuve 			return ret;
2354d82b2f9SHugo Villeneuve 
2364d82b2f9SHugo Villeneuve 		return IIO_VAL_INT;
2374d82b2f9SHugo Villeneuve 	case IIO_CHAN_INFO_SCALE:
2384d82b2f9SHugo Villeneuve 		vref_uv = regulator_get_voltage(data->vref_reg);
2394d82b2f9SHugo Villeneuve 		if (vref_uv < 0)
2404d82b2f9SHugo Villeneuve 			return vref_uv;
2414d82b2f9SHugo Villeneuve 
2424d82b2f9SHugo Villeneuve 		*val =  vref_uv / 1000; /* Convert reg voltage to mV */
2434d82b2f9SHugo Villeneuve 		*val2 = ADS7924_BITS;
2444d82b2f9SHugo Villeneuve 		return IIO_VAL_FRACTIONAL_LOG2;
2454d82b2f9SHugo Villeneuve 	default:
2464d82b2f9SHugo Villeneuve 		return -EINVAL;
2474d82b2f9SHugo Villeneuve 	}
2484d82b2f9SHugo Villeneuve }
2494d82b2f9SHugo Villeneuve 
2504d82b2f9SHugo Villeneuve static const struct iio_info ads7924_info = {
2514d82b2f9SHugo Villeneuve 	.read_raw = ads7924_read_raw,
2524d82b2f9SHugo Villeneuve };
2534d82b2f9SHugo Villeneuve 
ads7924_get_channels_config(struct i2c_client * client,struct iio_dev * indio_dev)2544d82b2f9SHugo Villeneuve static int ads7924_get_channels_config(struct i2c_client *client,
2554d82b2f9SHugo Villeneuve 				       struct iio_dev *indio_dev)
2564d82b2f9SHugo Villeneuve {
2574d82b2f9SHugo Villeneuve 	struct ads7924_data *priv = iio_priv(indio_dev);
2584d82b2f9SHugo Villeneuve 	struct device *dev = priv->dev;
2594d82b2f9SHugo Villeneuve 	struct fwnode_handle *node;
2604d82b2f9SHugo Villeneuve 	int num_channels = 0;
2614d82b2f9SHugo Villeneuve 
2624d82b2f9SHugo Villeneuve 	device_for_each_child_node(dev, node) {
2634d82b2f9SHugo Villeneuve 		u32 pval;
2644d82b2f9SHugo Villeneuve 		unsigned int channel;
2654d82b2f9SHugo Villeneuve 
2664d82b2f9SHugo Villeneuve 		if (fwnode_property_read_u32(node, "reg", &pval)) {
2674d82b2f9SHugo Villeneuve 			dev_err(dev, "invalid reg on %pfw\n", node);
2684d82b2f9SHugo Villeneuve 			continue;
2694d82b2f9SHugo Villeneuve 		}
2704d82b2f9SHugo Villeneuve 
2714d82b2f9SHugo Villeneuve 		channel = pval;
2724d82b2f9SHugo Villeneuve 		if (channel >= ADS7924_CHANNELS) {
2734d82b2f9SHugo Villeneuve 			dev_err(dev, "invalid channel index %d on %pfw\n",
2744d82b2f9SHugo Villeneuve 				channel, node);
2754d82b2f9SHugo Villeneuve 			continue;
2764d82b2f9SHugo Villeneuve 		}
2774d82b2f9SHugo Villeneuve 
2784d82b2f9SHugo Villeneuve 		num_channels++;
2794d82b2f9SHugo Villeneuve 	}
2804d82b2f9SHugo Villeneuve 
2814d82b2f9SHugo Villeneuve 	if (!num_channels)
2824d82b2f9SHugo Villeneuve 		return -EINVAL;
2834d82b2f9SHugo Villeneuve 
2844d82b2f9SHugo Villeneuve 	return 0;
2854d82b2f9SHugo Villeneuve }
2864d82b2f9SHugo Villeneuve 
ads7924_set_conv_mode(struct ads7924_data * data,int mode)2874d82b2f9SHugo Villeneuve static int ads7924_set_conv_mode(struct ads7924_data *data, int mode)
2884d82b2f9SHugo Villeneuve {
2894d82b2f9SHugo Villeneuve 	int ret;
2904d82b2f9SHugo Villeneuve 	unsigned int mode_field;
2914d82b2f9SHugo Villeneuve 	struct device *dev = data->dev;
2924d82b2f9SHugo Villeneuve 
2934d82b2f9SHugo Villeneuve 	/*
2944d82b2f9SHugo Villeneuve 	 * When switching between modes, be sure to first select the Awake mode
2954d82b2f9SHugo Villeneuve 	 * and then switch to the desired mode. This procedure ensures the
2964d82b2f9SHugo Villeneuve 	 * internal control logic is properly synchronized.
2974d82b2f9SHugo Villeneuve 	 */
2984d82b2f9SHugo Villeneuve 	if (mode != ADS7924_MODECNTRL_IDLE) {
2994d82b2f9SHugo Villeneuve 		mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK,
3004d82b2f9SHugo Villeneuve 					ADS7924_MODECNTRL_AWAKE);
3014d82b2f9SHugo Villeneuve 
3024d82b2f9SHugo Villeneuve 		ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG,
3034d82b2f9SHugo Villeneuve 					 ADS7924_MODECNTRL_MODE_MASK,
3044d82b2f9SHugo Villeneuve 					 mode_field);
3054d82b2f9SHugo Villeneuve 		if (ret) {
3064d82b2f9SHugo Villeneuve 			dev_err(dev, "failed to set awake mode (%pe)\n",
3074d82b2f9SHugo Villeneuve 				ERR_PTR(ret));
3084d82b2f9SHugo Villeneuve 			return ret;
3094d82b2f9SHugo Villeneuve 		}
3104d82b2f9SHugo Villeneuve 	}
3114d82b2f9SHugo Villeneuve 
3124d82b2f9SHugo Villeneuve 	mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK, mode);
3134d82b2f9SHugo Villeneuve 
3144d82b2f9SHugo Villeneuve 	ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG,
3154d82b2f9SHugo Villeneuve 				 ADS7924_MODECNTRL_MODE_MASK, mode_field);
3164d82b2f9SHugo Villeneuve 	if (ret)
3174d82b2f9SHugo Villeneuve 		dev_err(dev, "failed to set mode %d (%pe)\n", mode,
3184d82b2f9SHugo Villeneuve 			ERR_PTR(ret));
3194d82b2f9SHugo Villeneuve 
3204d82b2f9SHugo Villeneuve 	return ret;
3214d82b2f9SHugo Villeneuve }
3224d82b2f9SHugo Villeneuve 
ads7924_reset(struct iio_dev * indio_dev)3234d82b2f9SHugo Villeneuve static int ads7924_reset(struct iio_dev *indio_dev)
3244d82b2f9SHugo Villeneuve {
3254d82b2f9SHugo Villeneuve 	struct ads7924_data *data = iio_priv(indio_dev);
3264d82b2f9SHugo Villeneuve 
3274d82b2f9SHugo Villeneuve 	if (data->reset_gpio) {
3284d82b2f9SHugo Villeneuve 		gpiod_set_value(data->reset_gpio, 1); /* Assert. */
3294d82b2f9SHugo Villeneuve 		/* Educated guess: assert time not specified in datasheet... */
3304d82b2f9SHugo Villeneuve 		mdelay(100);
3314d82b2f9SHugo Villeneuve 		gpiod_set_value(data->reset_gpio, 0); /* Deassert. */
3324d82b2f9SHugo Villeneuve 		return 0;
3334d82b2f9SHugo Villeneuve 	}
3344d82b2f9SHugo Villeneuve 
3354d82b2f9SHugo Villeneuve 	/*
3364d82b2f9SHugo Villeneuve 	 * A write of 10101010 to this register will generate a
3374d82b2f9SHugo Villeneuve 	 * software reset of the ADS7924.
3384d82b2f9SHugo Villeneuve 	 */
3394d82b2f9SHugo Villeneuve 	return regmap_write(data->regmap, ADS7924_RESET_REG, 0b10101010);
3404d82b2f9SHugo Villeneuve };
3414d82b2f9SHugo Villeneuve 
ads7924_reg_disable(void * data)3424d82b2f9SHugo Villeneuve static void ads7924_reg_disable(void *data)
3434d82b2f9SHugo Villeneuve {
3444d82b2f9SHugo Villeneuve 	regulator_disable(data);
3454d82b2f9SHugo Villeneuve }
3464d82b2f9SHugo Villeneuve 
ads7924_set_idle_mode(void * data)3474d82b2f9SHugo Villeneuve static void ads7924_set_idle_mode(void *data)
3484d82b2f9SHugo Villeneuve {
3494d82b2f9SHugo Villeneuve 	ads7924_set_conv_mode(data, ADS7924_MODECNTRL_IDLE);
3504d82b2f9SHugo Villeneuve }
3514d82b2f9SHugo Villeneuve 
ads7924_probe(struct i2c_client * client)3524d82b2f9SHugo Villeneuve static int ads7924_probe(struct i2c_client *client)
3534d82b2f9SHugo Villeneuve {
3544d82b2f9SHugo Villeneuve 	struct iio_dev *indio_dev;
3554d82b2f9SHugo Villeneuve 	struct ads7924_data *data;
3564d82b2f9SHugo Villeneuve 	struct device *dev = &client->dev;
3574d82b2f9SHugo Villeneuve 	int ret;
3584d82b2f9SHugo Villeneuve 
3594d82b2f9SHugo Villeneuve 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
3604d82b2f9SHugo Villeneuve 	if (!indio_dev)
3614d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, -ENOMEM,
3624d82b2f9SHugo Villeneuve 				     "failed to allocate iio device\n");
3634d82b2f9SHugo Villeneuve 
3644d82b2f9SHugo Villeneuve 	data = iio_priv(indio_dev);
3654d82b2f9SHugo Villeneuve 
3664d82b2f9SHugo Villeneuve 	data->dev = dev;
3674d82b2f9SHugo Villeneuve 
3684d82b2f9SHugo Villeneuve 	/* Initialize the reset GPIO as output with an initial value of 0. */
3694d82b2f9SHugo Villeneuve 	data->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
3704d82b2f9SHugo Villeneuve 	if (IS_ERR(data->reset_gpio))
3714d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, PTR_ERR(data->reset_gpio),
3724d82b2f9SHugo Villeneuve 				     "failed to get request reset GPIO\n");
3734d82b2f9SHugo Villeneuve 
3744d82b2f9SHugo Villeneuve 	mutex_init(&data->lock);
3754d82b2f9SHugo Villeneuve 
3764d82b2f9SHugo Villeneuve 	indio_dev->name = "ads7924";
3774d82b2f9SHugo Villeneuve 	indio_dev->modes = INDIO_DIRECT_MODE;
3784d82b2f9SHugo Villeneuve 
3794d82b2f9SHugo Villeneuve 	indio_dev->channels = ads7924_channels;
3804d82b2f9SHugo Villeneuve 	indio_dev->num_channels = ARRAY_SIZE(ads7924_channels);
3814d82b2f9SHugo Villeneuve 	indio_dev->info = &ads7924_info;
3824d82b2f9SHugo Villeneuve 
3834d82b2f9SHugo Villeneuve 	ret = ads7924_get_channels_config(client, indio_dev);
3844d82b2f9SHugo Villeneuve 	if (ret < 0)
3854d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, ret,
3864d82b2f9SHugo Villeneuve 				     "failed to get channels configuration\n");
3874d82b2f9SHugo Villeneuve 
3884d82b2f9SHugo Villeneuve 	data->regmap = devm_regmap_init_i2c(client, &ads7924_regmap_config);
3894d82b2f9SHugo Villeneuve 	if (IS_ERR(data->regmap))
3904d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, PTR_ERR(data->regmap),
3914d82b2f9SHugo Villeneuve 				     "failed to init regmap\n");
3924d82b2f9SHugo Villeneuve 
3934d82b2f9SHugo Villeneuve 	data->vref_reg = devm_regulator_get(dev, "vref");
3944d82b2f9SHugo Villeneuve 	if (IS_ERR(data->vref_reg))
3954d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, PTR_ERR(data->vref_reg),
3964d82b2f9SHugo Villeneuve 				     "failed to get vref regulator\n");
3974d82b2f9SHugo Villeneuve 
3984d82b2f9SHugo Villeneuve 	ret = regulator_enable(data->vref_reg);
3994d82b2f9SHugo Villeneuve 	if (ret)
4004d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, ret,
4014d82b2f9SHugo Villeneuve 				     "failed to enable regulator\n");
4024d82b2f9SHugo Villeneuve 
4034d82b2f9SHugo Villeneuve 	ret = devm_add_action_or_reset(dev, ads7924_reg_disable, data->vref_reg);
4044d82b2f9SHugo Villeneuve 	if (ret)
4054d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, ret,
4064d82b2f9SHugo Villeneuve 				     "failed to add regulator disable action\n");
4074d82b2f9SHugo Villeneuve 
4084d82b2f9SHugo Villeneuve 	ret = ads7924_reset(indio_dev);
4094d82b2f9SHugo Villeneuve 	if (ret < 0)
4104d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, ret,
4114d82b2f9SHugo Villeneuve 				     "failed to reset device\n");
4124d82b2f9SHugo Villeneuve 
4134d82b2f9SHugo Villeneuve 	ret = ads7924_set_conv_mode(data, ADS7924_MODECNTRL_AUTO_SCAN);
4144d82b2f9SHugo Villeneuve 	if (ret)
4154d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, ret,
4164d82b2f9SHugo Villeneuve 				     "failed to set conversion mode\n");
4174d82b2f9SHugo Villeneuve 
4184d82b2f9SHugo Villeneuve 	ret = devm_add_action_or_reset(dev, ads7924_set_idle_mode, data);
4194d82b2f9SHugo Villeneuve 	if (ret)
4204d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, ret,
4214d82b2f9SHugo Villeneuve 				     "failed to add idle mode action\n");
4224d82b2f9SHugo Villeneuve 
4234d82b2f9SHugo Villeneuve 	/* Use minimum signal acquire time. */
4244d82b2f9SHugo Villeneuve 	ret = regmap_update_bits(data->regmap, ADS7924_ACQCONFIG_REG,
4254d82b2f9SHugo Villeneuve 				 ADS7924_ACQTIME_MASK,
4264d82b2f9SHugo Villeneuve 				 FIELD_PREP(ADS7924_ACQTIME_MASK, 0));
4274d82b2f9SHugo Villeneuve 	if (ret < 0)
4284d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, ret,
4294d82b2f9SHugo Villeneuve 				     "failed to configure signal acquire time\n");
4304d82b2f9SHugo Villeneuve 
4314d82b2f9SHugo Villeneuve 	/* Disable power-up time. */
4324d82b2f9SHugo Villeneuve 	ret = regmap_update_bits(data->regmap, ADS7924_PWRCONFIG_REG,
4334d82b2f9SHugo Villeneuve 				 ADS7924_PWRUPTIME_MASK,
4344d82b2f9SHugo Villeneuve 				 FIELD_PREP(ADS7924_PWRUPTIME_MASK, 0));
4354d82b2f9SHugo Villeneuve 	if (ret < 0)
4364d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, ret,
4374d82b2f9SHugo Villeneuve 				     "failed to configure power-up time\n");
4384d82b2f9SHugo Villeneuve 
4394d82b2f9SHugo Villeneuve 	data->conv_invalid = true;
4404d82b2f9SHugo Villeneuve 
4414d82b2f9SHugo Villeneuve 	ret = devm_iio_device_register(dev, indio_dev);
4424d82b2f9SHugo Villeneuve 	if (ret < 0)
4434d82b2f9SHugo Villeneuve 		return dev_err_probe(dev, ret,
4444d82b2f9SHugo Villeneuve 				     "failed to register IIO device\n");
4454d82b2f9SHugo Villeneuve 
4464d82b2f9SHugo Villeneuve 	return 0;
4474d82b2f9SHugo Villeneuve }
4484d82b2f9SHugo Villeneuve 
4494d82b2f9SHugo Villeneuve static const struct i2c_device_id ads7924_id[] = {
450*4391affaSUwe Kleine-König 	{ "ads7924" },
4514d82b2f9SHugo Villeneuve 	{}
4524d82b2f9SHugo Villeneuve };
4534d82b2f9SHugo Villeneuve MODULE_DEVICE_TABLE(i2c, ads7924_id);
4544d82b2f9SHugo Villeneuve 
4554d82b2f9SHugo Villeneuve static const struct of_device_id ads7924_of_match[] = {
4564d82b2f9SHugo Villeneuve 	{ .compatible = "ti,ads7924", },
4574d82b2f9SHugo Villeneuve 	{}
4584d82b2f9SHugo Villeneuve };
4594d82b2f9SHugo Villeneuve MODULE_DEVICE_TABLE(of, ads7924_of_match);
4604d82b2f9SHugo Villeneuve 
4614d82b2f9SHugo Villeneuve static struct i2c_driver ads7924_driver = {
4624d82b2f9SHugo Villeneuve 	.driver = {
4634d82b2f9SHugo Villeneuve 		.name = "ads7924",
4644d82b2f9SHugo Villeneuve 		.of_match_table = ads7924_of_match,
4654d82b2f9SHugo Villeneuve 	},
4667cf15f42SUwe Kleine-König 	.probe		= ads7924_probe,
4674d82b2f9SHugo Villeneuve 	.id_table	= ads7924_id,
4684d82b2f9SHugo Villeneuve };
4694d82b2f9SHugo Villeneuve 
4704d82b2f9SHugo Villeneuve module_i2c_driver(ads7924_driver);
4714d82b2f9SHugo Villeneuve 
4724d82b2f9SHugo Villeneuve MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@dimonoff.com>");
4734d82b2f9SHugo Villeneuve MODULE_DESCRIPTION("Texas Instruments ADS7924 ADC I2C driver");
4744d82b2f9SHugo Villeneuve MODULE_LICENSE("GPL");
475