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/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c17 * NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
26 * ref_freq = 28.636360 MHz
28 * ref_freq = 28.636363 MHz
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
47 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
52 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
53 * 196.6 MHz pre-postdivide in cx25840_set_audclk_freq()
54 * FIXME < 200 MHz is out of specified valid range in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
84 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
57 /* frequency 5600MHz */
[all …]
/linux/arch/arm/mach-omap2/
H A Dtimer.c53 * at a rate of 6.144 MHz. Because the device operates on different clocks
86 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
98 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
128 num = 384; in realtime_counter_init()
137 /* Program it for 38.4 MHz */ in realtime_counter_init()
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-data-modul-edm-sbc.dts281 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
416 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
458 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
469 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
819 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
833 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
864 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
881 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_consts.h46 .onestep = 0x30000 /* 384 */
293 /* ICE_TSPLL_FREQ_25_000 -> 25 MHz */
296 823437500, /* 823.4375 MHz PLL */
301 /* ICE_TSPLL_FREQ_122_880 -> 122.88 MHz */
304 783360000, /* 783.36 MHz */
309 /* ICE_TSPLL_FREQ_125_000 -> 125 MHz */
312 796875000, /* 796.875 MHz */
317 /* ICE_TSPLL_FREQ_153_600 -> 153.6 MHz */
320 816000000, /* 816 MHz */
325 /* ICE_TSPLL_FREQ_156_250 -> 156.25 MHz */
[all …]
/linux/include/sound/
H A Dak4113.h133 /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
135 /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
147 /* 11.2896 MHz ref. Xtal freq. */
149 /* 12.288 MHz ref. Xtal freq. */
151 /* 24.576 MHz ref. Xtal freq. */
163 /* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */
/linux/drivers/media/dvb-frontends/
H A Dmxl692_defs.h22 #define MXL_EAGLE_ATSC_DFE_TAPS_LENGTH 384
295 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_0_772MHZ, /* ANSI/SCTE 55-2 0.772 MHz */
296 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_024MHZ, /* ANSI/SCTE 55-1 1.024 MHz */
297 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_544MHZ, /* ANSI/SCTE 55-2 1.544 MHz */
H A Dau8522_dig.c158 { 24, 384 },
261 dprintk("%s() %s MHz\n", __func__, ifmhz); in au8522_set_if()
888 .frequency_min_hz = 54 * MHz,
889 .frequency_max_hz = 858 * MHz,
H A Dstv0900_core.c554 Tuner_Frequency(MHz) = Regs / 64 in stv0900_get_freq_auto()
555 Tuner_granularity(MHz) = Regs / 2048 in stv0900_get_freq_auto()
556 real_Tuner_Frequency = Tuner_Frequency(MHz) - Tuner_granularity(MHz) in stv0900_get_freq_auto()
577 Tuner_frequency_reg= Frequency(MHz)*64 in stv0900_set_tuner_auto()
584 /* Low Pass Filter = BW /2 (MHz)*/ in stv0900_set_tuner_auto()
756 snrlcl = (snrlcl + 30) * 384; in stv0900_read_snr()
1422 stv0900_write_reg(intp, R0900_P1_TNRXTAL, 27); /* 27MHz */ in stv0900_init_internal()
1452 stv0900_write_reg(intp, R0900_P2_TNRXTAL, 27); /* 27MHz */ in stv0900_init_internal()
1868 .frequency_min_hz = 950 * MHz,
1869 .frequency_max_hz = 2150 * MHz,
/linux/sound/pci/ice1712/
H A Denvy24ht.h51 #define VT1724_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
52 #define VT1724_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
H A Dice1712.h178 #define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
179 #define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller-common.yaml85 - for eMMC, the maximum supported frequency is 200MHz,
87 frequency of 208MHz,
89 384MHz.
/linux/drivers/video/fbdev/
H A Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
347 {512, 384, 60, 1},
348 {512, 384, 60},
H A Dgbefb.c87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
148 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
467 * GBE crystal runs at 20Mhz or 27Mhz in compute_gbe_timing()
469 * fvco = pll_m * 20Mhz / pll_n in compute_gbe_timing()
695 <---- 512 ----><128|384 offscreen> in gbefb_set_par()
/linux/sound/soc/codecs/
H A Dtlv320aic23.c193 * 11.2896 Mhz /128 = *88.2k /192 = 58.8k
194 * 12.0000 Mhz /125 = *96k /136 = 88.235K
195 * 12.2880 Mhz /128 = *96k /192 = 64k
196 * 16.9344 Mhz /128 = 132.3k /192 = *88.2k
197 * 18.4320 Mhz /128 = 144k /192 = *96k
201 * Normal BOSR 0-256/2 = 128, 1-384/2 = 192
H A Dcs48l32.c257 "384kHz",
277 0x06, /* 384kHz */
670 "384kHz", "768kHz", "1.536MHz", "2.048MHz", "2.4576MHz", "3.072MHz", "6.144MHz",
786 "3.072MHz", "2.048MHz", "1.536MHz", "768kHz",
1396 freq /= 15625; /* convert to 1/64ths of 1MHz */ in cs48l32_get_dspclk_setting()
1799 cs48l32_fll_err(fll, "Can't scale %dMHz to <=13MHz\n", ref_in); in cs48l32_fllhj_validate()
/linux/drivers/clk/
H A Dclk-aspeed.c137 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ in aspeed_ast2400_calc_pll()
467 /* RMII 50MHz RCLK */ in aspeed_clk_probe()
473 /* RMII1 50MHz (RCLK) output enable */ in aspeed_clk_probe()
481 /* RMII2 50MHz (RCLK) output enable */ in aspeed_clk_probe()
508 /* Fixed 24MHz clock */ in aspeed_clk_probe()
588 {384, 360, 336, 408}, in aspeed_ast2400_cc()
594 * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by in aspeed_ast2400_cc()
610 pr_debug("clkin @%u MHz\n", clkin / 1000000); in aspeed_ast2400_cc()
656 /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ in aspeed_ast2500_cc()
663 pr_debug("clkin @%u MHz\n", freq / 1000000); in aspeed_ast2500_cc()
/linux/sound/soc/atmel/
H A Datmel-i2s.c170 /* mck = 6.144Mhz */
173 /* mck = 12.288MHz */
176 { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */
182 /* mck = 11.2896MHz */
/linux/drivers/mfd/
H A Dsm501.c86 #define MHZ (1000 * 1000) macro
105 [15] = 384,
121 pll2 = 288 * MHZ; in decode_div()
126 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
[all …]
/linux/arch/mips/cavium-octeon/executive/
H A Docteon-model.c458 int fuse_base = 384 / 8; in octeon_model_get_string_buffer()
501 * - FREQ = Current frequency in Mhz
/linux/drivers/media/i2c/
H A Dtw9910.c132 #define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
134 /* Must use 24.54MHz for 60Hz field rate */
135 /* source or 29.5MHz for 50Hz field rate */
296 .width = 384,
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi159 regulator-settling-time-up-us = <384>;
523 * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the
/linux/include/dt-bindings/clock/
H A Dtegra234-clock.h200 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
206 /** Fixed frequency 960MHz PLL for USB and EAVB */
539 /** @brief Fixed 48MHz clock divided down from utmipll */
541 /** @brief Fixed 480MHz clock divided down from utmipll */
712 #define TEGRA234_CLK_MGBE1_TX_PCS 384U
/linux/drivers/media/pci/cobalt/
H A Dcobalt-cpld.c173 { 380, 5, 76 }, { 384, 4, 96 }, { 390, 5, 78 },
274 then a strange frequency is set (156.412034 MHz, or register values in cobalt_cpld_set_freq()
/linux/drivers/net/wireless/ath/ath5k/
H A Dath5k.h232 /* Used to calculate tx time for non 5/10/40MHz
236 /* Preamble time for 40MHz (turbo) operation (min ?) */
241 /* Rx latency for 5 and 10MHz operation (max ?) */
246 #define AR5K_INIT_TX_LAT_BG 384
247 /* Tx latency for 40MHz (turbo) operation (min ?) */
386 * get a mode similar to XR by using 5MHz bwmode.
434 * get a mode similar to TURBO by using 40MHz bwmode.
481 * @AR5K_BWMODE_DEFAULT: 20MHz, default operation

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