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/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c17 * NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
26 * ref_freq = 28.636360 MHz
28 * ref_freq = 28.636363 MHz
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
47 * 432 MHz pre-postdivide in cx25840_set_audclk_freq()
52 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
53 * 196.6 MHz pre-postdivide in cx25840_set_audclk_freq()
54 * FIXME < 200 MHz is out of specified valid range in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
84 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
[all …]
/linux/drivers/media/pci/cx18/
H A Dcx18-av-audio.c25 * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz in set_audclk_freq()
41 * crystal value at all, it will assume 28.636360 MHz, the crystal in set_audclk_freq()
44 * xtal_freq = 28.636360 MHz in set_audclk_freq()
49 * Below I aim to run the PLLs' VCOs near 400 MHz to minimize error. in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
82 /* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */ in set_audclk_freq()
101 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
105 /* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/ in set_audclk_freq()
117 /* AUD_COUNT = 0x92ff = 49 samples * 2 * 384 - 1 */ in set_audclk_freq()
[all …]
H A Dcx18-av-core.c91 * 28.636360 MHz. in cx18_av_init()
92 * Aim to run the PLLs' VCOs near 400 MHz to minimize errors. in cx18_av_init()
102 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */ in cx18_av_init()
106 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/ in cx18_av_init()
281 * 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b in cx18_av_std_setup()
452 CX18_DEBUG_INFO_DEV(sd, "Video PLL = %d.%06d MHz\n", in cx18_av_std_setup()
465 "Chroma sub-carrier initial freq = %d.%06d MHz\n", in cx18_av_std_setup()
1101 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break; in log_audio_status()
1107 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break; in log_audio_status()
1131 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break; in log_audio_status()
[all …]
/linux/sound/soc/codecs/
H A Dcs42xx8.c188 * 0 | 0 | 0 |1.029MHz to 12.8MHz | 256 | 128 | 64 |
189 * 0 | 0 | 1 |1.536MHz to 19.2MHz | 384 | 192 | 96 |
190 * 0 | 1 | 0 |2.048MHz to 25.6MHz | 512 | 256 | 128 |
191 * 0 | 1 | 1 |3.072MHz to 38.4MHz | 768 | 384 | 192 |
192 * 1 | x | x |4.096MHz to 51.2MHz |1024 | 512 | 256 |
196 { 2, 1536000, 19200000, {384, 192, 96} },
198 { 6, 3072000, 38400000, {768, 384, 192} },
H A Dtlv320aic23.c193 * 11.2896 Mhz /128 = *88.2k /192 = 58.8k
194 * 12.0000 Mhz /125 = *96k /136 = 88.235K
195 * 12.2880 Mhz /128 = *96k /192 = 64k
196 * 16.9344 Mhz /128 = 132.3k /192 = *88.2k
197 * 18.4320 Mhz /128 = 144k /192 = *96k
201 * Normal BOSR 0-256/2 = 128, 1-384/2 = 192
/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
57 /* frequency 5600MHz */
[all …]
/linux/drivers/video/fbdev/
H A Dmacmodes.c36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
37 "mac2", 60, 512, 384, 63828, 80, 16, 19, 1, 32, 3,
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
64 /* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
68 /* 832x624, 75Hz, Non-Interlaced (57.6 MHz dotclock) */
[all …]
H A Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
347 {512, 384, 60, 1},
348 {512, 384, 60},
/linux/arch/arm/mach-omap2/
H A Dtimer.c53 * at a rate of 6.144 MHz. Because the device operates on different clocks
86 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 in realtime_counter_init()
98 * should compensate to avoid the 570ppm (at 20MHz, much worse in realtime_counter_init()
128 num = 384; in realtime_counter_init()
137 /* Program it for 38.4 MHz */ in realtime_counter_init()
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-data-modul-edm-sbc.dts281 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
416 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
458 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
469 /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
819 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
833 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
864 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
881 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
/linux/sound/soc/samsung/
H A Dsmdk_wm8994.c31 /* SMDK has a 16.934MHZ crystal attached to WM8994 */
42 /* AIF1CLK should be >=3MHz for optimal performance */ in smdk_hw_params()
44 pll_out = params_rate(params) * 384; in smdk_hw_params()
H A Darndale.c62 /* Ensure AIF1CLK is >= 3 MHz for optimal performance */ in arndale_wm1811_hw_params()
64 rfs = 384; in arndale_wm1811_hw_params()
/linux/Documentation/admin-guide/media/
H A Dsi4713.rst65 Frequency: 1408000 (88.000000 MHz)
70 Frequency range : 76.0 MHz - 108.0 MHz
83 rds_radio_text (str) : min=0 max=384 step=32 value=''
/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_consts.h91 .onestep = 0x30000 /* 384 */
338 /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
341 823437500, /* 823.4375 MHz PLL */
348 /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
351 783360000, /* 783.36 MHz */
358 /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
361 796875000, /* 796.875 MHz */
368 /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
371 816000000, /* 816 MHz */
378 /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
[all …]
/linux/include/sound/
H A Dak4113.h133 /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
135 /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
147 /* 11.2896 MHz ref. Xtal freq. */
149 /* 12.288 MHz ref. Xtal freq. */
151 /* 24.576 MHz ref. Xtal freq. */
163 /* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */
/linux/drivers/media/dvb-frontends/
H A Dmxl692_defs.h22 #define MXL_EAGLE_ATSC_DFE_TAPS_LENGTH 384
295 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_0_772MHZ, /* ANSI/SCTE 55-2 0.772 MHz */
296 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_024MHZ, /* ANSI/SCTE 55-1 1.024 MHz */
297 MXL_EAGLE_OOB_DEMOD_SYMB_RATE_1_544MHZ, /* ANSI/SCTE 55-2 1.544 MHz */
/linux/sound/pci/ice1712/
H A Denvy24ht.h51 #define VT1724_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
52 #define VT1724_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
H A Dice1712.h178 #define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */
179 #define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */
/linux/drivers/mtd/nand/onenand/
H A Donenand_omap2.c379 count < 384 || mtd->oops_panic_write) in omap2_onenand_read_bufferram()
426 count < 384 || mtd->oops_panic_write) in omap2_onenand_write_bufferram()
542 default: /* 40 MHz or lower */ in omap2_onenand_probe()
558 dev_info(dev, "optimized timings for %d MHz\n", freq); in omap2_onenand_probe()
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller.yaml93 - for eMMC, the maximum supported frequency is 200MHz,
95 frequency of 208MHz,
97 384MHz.
/linux/drivers/clk/
H A Dclk-aspeed.c137 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ in aspeed_ast2400_calc_pll()
467 /* RMII 50MHz RCLK */ in aspeed_clk_probe()
473 /* RMII1 50MHz (RCLK) output enable */ in aspeed_clk_probe()
481 /* RMII2 50MHz (RCLK) output enable */ in aspeed_clk_probe()
508 /* Fixed 24MHz clock */ in aspeed_clk_probe()
588 {384, 360, 336, 408}, in aspeed_ast2400_cc()
594 * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by in aspeed_ast2400_cc()
610 pr_debug("clkin @%u MHz\n", clkin / 1000000); in aspeed_ast2400_cc()
656 /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ in aspeed_ast2500_cc()
663 pr_debug("clkin @%u MHz\n", freq / 1000000); in aspeed_ast2500_cc()
/linux/sound/soc/atmel/
H A Datmel-i2s.c170 /* mck = 6.144Mhz */
173 /* mck = 12.288MHz */
176 { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */
182 /* mck = 11.2896MHz */
/linux/drivers/mfd/
H A Dsm501.c86 #define MHZ (1000 * 1000) macro
105 [15] = 384,
121 pll2 = 288 * MHZ; in decode_div()
126 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
[all …]
/linux/arch/mips/cavium-octeon/executive/
H A Docteon-model.c457 int fuse_base = 384 / 8; in octeon_model_get_string_buffer()
500 * - FREQ = Current frequency in Mhz
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-buttress.c808 * Example (TSC clock frequency is 19.2MHz): in ipu6_buttress_tsc_ticks_to_ns()
809 * ns = ticks * 1000 000 000 / 19.2Mhz in ipu6_buttress_tsc_ticks_to_ns()
876 b->ref_clk = 384; in ipu6_buttress_init()
880 "Unsupported ref clock, use 19.2Mhz by default.\n"); in ipu6_buttress_init()

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