384MHz (full) in projects: linux - OpenGrok search results

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Searched +full:384 +full:mhz (Results 1 – 13 of 13) sorted by relevance

/illumos-gate/usr/src/uts/common/io/mwl/
H A D	mwl_var.h	`283 uint16_t ic_freq; /* setting in Mhz / 684 CTRY_COTE_DIVOIRE = 384, 852 SKU_SR9 = 0x0298, / Ubiquiti SR9 (900MHz/GSM) / 853 SKU_XR9 = 0x0299, / Ubiquiti XR9 (900MHz/GSM) / 854 SKU_GZ901 = 0x029a, / Zcomax GZ-901 (900MHz/GSM) / 868 DOMAIN_CODE_MKK2 = 0x41, / Japan w/ 10MHz chan spacing */`
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/
H A D	ecore_init_fw_funcs.c	`51 { 400, 336, 352, 304, 304, 384, 416, 352}, /* region 3 offsets / 96 / Period in 25MHz cycles / 889 / Period in 25MHz cycles */`
/illumos-gate/usr/src/uts/common/io/iwk/
H A D	iwk_hw.h	`795 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad. 1546 * 40 MHz wide (.11n fat) channels are listed separately from 20 MHz 1607 * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel 1608 * widths and 40 Mhz (.11n fat) channel widths; there is no separate 1625 * on frequency (5 MHz between each channel number), this is equivalent`
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D	57712_reg.h	1326 …EMPTY_1_SIZE 384 5964 …manual setting has affect when bit#0 = 1: 0-select USPLL clock; 1-select 25Mhz (ref clock); Reset … 6084 …W) expecting activity in the near future and the SM should begin exiting EEE LPI mode. Clock 25MHz. 6086 …W) expecting activity in the near future and the SM should begin exiting EEE LPI mode. Clock 25MHz. 6088 … activity in the near future and the SM should begin exiting L1 mode. Clock 25MHz. Global register. 6090 …0x1 Description: PCI SERDES alternate clock selector. When 0 - 250MHz. When 1 -25MHz. Global regi… 6094 …led by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk 25MHz. Reset on hard rese… 6096 …led by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk 25MHz. Reset on hard rese… 6098 …nabled by FW. When 0 indicates that the L1 mode is disabled by FW. Clock 25MHz. Global register. R… 6100 …ver. When 0 indicates that the EEE LPI mode is disabled by driver. Clock 25MHz. Reset on hard rese… [all …]
/illumos-gate/usr/src/uts/common/crypto/io/
H A D	dca.c	`1508 if (num <= 384) { in dca_padhalf() 1509 return (BITS2BYTES(384)); in dca_padhalf() 1671 * using 4 threads and 12032 byte data and 3DES on 900MHZ Sparc system, in dca_newreq()`
/illumos-gate/usr/src/data/hwdata/
H A D	usb.ids	`19034 076b OpenPCD 13.56MHz RFID Reader 19035 076c OpenPICC 13.56MHz RFID Simulator (native) 19323 0010 444MHz Radio Mesh Frontend 19324 0011 444MHz RF sniffer 19325 0012 870MHz Radio Mesh Frontend 19326 0013 870MHz RF sniffer 21526 0012 RF Sythesizer 250-4200MHz model SSG-4000LH 21999 0003 OpenPCD 2 RFID Reader for 13.56MHz 22005 0009 OpenPCD 2 RFID Reader for 13.56MHz 22296 9227 SA9227 384KHz audio controller [all …]`
/illumos-gate/usr/src/uts/intel/os/
H A D	cpuid.c	`6176 "x86 (%s %X family %d model %d step %d clock %d MHz)"; in cpuid_getidstr() 6178 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; in cpuid_getidstr() 6959 { 0x3d, 6, 64, 3841024, sl2_cache_str}, 7412 / cpu-mhz, and clock-frequency */ in cpuid_set_cpu_properties() 7417 "cpu-mhz", cpu_freq); in cpuid_set_cpu_properties()`
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_ah_compile15.h	128 …D_REG_FAST_66MHZ_CAP (0x1<<21) // PCI 66MHz Capability. 3616 …MHz core), then the core actually transmits SKP ordered sets once every 1537 symbol times. The val… 5164 …MHz. This value is used to provide a 1 us reference for counting time during low-power states with… 5940 …AX (0x1f<<0) // Counter of 25 MHz clks for the mininu… 5942 … (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz clks for the minimu… 5944 …MAX (0x1f<<9) // Counter of 25 MHz clks for the maximu… 5946 …X (0x7f<<14) // Counter of 25 MHz clks for the minimu… 5950 …the version.v b00 : lfclk = 25 MHz (default and compatible with older cores) b01 : lfclk = 50 MHz… 5952 … (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz clks for the minimu… 5959 … (0x3f<<0) // Number of clocks at 25 MHz to delay between th… [all …]
H A D	reg_addr_e5.h	125 …_66MHZ_CAP (0x1<<21) // PCI 66MHz Capability. 3390 …MHz core), then the core actually transmits SKP ordered sets once every 1537 symbol times. The val… 4986 …MHz. This value is used to provide a 1 us reference for counting time during low-power states with… 5760 … (0x1f<<0) // Counter of 25 MHz clks for the mininu… 5762 … (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz clks for the minimu… 5764 … (0x1f<<9) // Counter of 25 MHz clks for the maximu… 5766 … (0x7f<<14) // Counter of 25 MHz clks for the minimu… 5770 …the version.v b00 : lfclk = 25 MHz (default and compatible with older cores) b01 : lfclk = 50 MHz… 5772 … (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz clks for the minimu… 5779 … (0x3f<<0) // Number of clocks at 25 MHz to delay between th… [all …]
H A D	reg_addr_k2.h	125 …_66MHZ_CAP (0x1<<21) // PCI 66MHz Capability. 3390 …MHz core), then the core actually transmits SKP ordered sets once every 1537 symbol times. The val… 4986 …MHz. This value is used to provide a 1 us reference for counting time during low-power states with… 5760 … (0x1f<<0) // Counter of 25 MHz clks for the mininu… 5762 … (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz clks for the minimu… 5764 … (0x1f<<9) // Counter of 25 MHz clks for the maximu… 5766 … (0x7f<<14) // Counter of 25 MHz clks for the minimu… 5770 …the version.v b00 : lfclk = 25 MHz (default and compatible with older cores) b01 : lfclk = 50 MHz… 5772 … (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz clks for the minimu… 5779 … (0x3f<<0) // Number of clocks at 25 MHz to delay between th… [all …]
H A D	reg_addr_bb.h	125 …_66MHZ_CAP (0x1<<21) // PCI 66MHz Capability. 3390 …MHz core), then the core actually transmits SKP ordered sets once every 1537 symbol times. The val… 4986 …MHz. This value is used to provide a 1 us reference for counting time during low-power states with… 5760 … (0x1f<<0) // Counter of 25 MHz clks for the mininu… 5762 … (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz clks for the minimu… 5764 … (0x1f<<9) // Counter of 25 MHz clks for the maximu… 5766 … (0x7f<<14) // Counter of 25 MHz clks for the minimu… 5770 …the version.v b00 : lfclk = 25 MHz (default and compatible with older cores) b01 : lfclk = 50 MHz… 5772 … (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz clks for the minimu… 5779 … (0x3f<<0) // Number of clocks at 25 MHz to delay between th… [all …]
H A D	reg_addr.h	126 …_66MHZ_CAP_K2_E5 (0x1<<21) // PCI 66MHz Capability. 3391 …MHz core), then the core actually transmits SKP ordered sets once every 1537 symbol times. The val… 4987 …MHz. This value is used to provide a 1 us reference for counting time during low-power states with… 5761 … (0x1f<<0) // Counter of 25 MHz clks for the mininu… 5763 … (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz clks for the minimu… 5765 … (0x1f<<9) // Counter of 25 MHz clks for the maximu… 5767 … (0x7f<<14) // Counter of 25 MHz clks for the minimu… 5771 …the version.v b00 : lfclk = 25 MHz (default and compatible with older cores) b01 : lfclk = 50 MHz… 5773 … (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz clks for the minimu… 5780 … (0x3f<<0) // Number of clocks at 25 MHz to delay between th… [all …]
/illumos-gate/usr/src/uts/common/io/nxge/
H A D	nxge_rxdma.c	`2376 sw_offset_bytes = 384; in nxge_receive_packet() 3627 * granularity (1000) is 3 microseconds running at 300MHz. in nxge_map_rxdma_channel_cfg_ring()`