Lines Matching +full:384 +full:mhz

86 #define MHZ (1000 * 1000)  macro
105 	[15]		= 384,
121 		pll2 = 288 * MHZ;  in decode_div()
126 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
144 		pll2 = 336 * MHZ;  in sm501_dump_clk()
147 		pll2 = 288 * MHZ;  in sm501_dump_clk()
150 		pll2 = 240 * MHZ;  in sm501_dump_clk()
153 		pll2 = 192 * MHZ;  in sm501_dump_clk()
157 	sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;  in sm501_dump_clk()
160 	sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;  in sm501_dump_clk()
166 	dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",  in sm501_dump_clk()
172 		 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "  in sm501_dump_clk()
181 		"P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "  in sm501_dump_clk()
482  * achieved using the 288MHz and 336MHz PLLs.
493 	/* Try 288MHz and 336MHz clocks. */  in sm501_select_clock()
1529 	/* Errata AB-3 says that 72MHz is the fastest available
1530 	 * for 33MHZ PCI with proper bus-mastering operation */
1532 	.mclk		= 72 * MHZ,
1533 	.m1xclk		= 144 * MHZ,