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/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h616-cpu-opp.dtsi13 clock-latency-ns = <244144>; /* 8 32k periods */
20 clock-latency-ns = <244144>; /* 8 32k periods */
27 clock-latency-ns = <244144>; /* 8 32k periods */
35 clock-latency-ns = <244144>; /* 8 32k periods */
42 clock-latency-ns = <244144>; /* 8 32k periods */
54 clock-latency-ns = <244144>; /* 8 32k periods */
61 clock-latency-ns = <244144>; /* 8 32k periods */
71 clock-latency-ns = <244144>; /* 8 32k periods */
83 clock-latency-ns = <244144>; /* 8 32k periods */
90 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
H A Dsun50i-h5-cpu-opp.dtsi12 clock-latency-ns = <244144>; /* 8 32k periods */
18 clock-latency-ns = <244144>; /* 8 32k periods */
24 clock-latency-ns = <244144>; /* 8 32k periods */
30 clock-latency-ns = <244144>; /* 8 32k periods */
36 clock-latency-ns = <244144>; /* 8 32k periods */
42 clock-latency-ns = <244144>; /* 8 32k periods */
48 clock-latency-ns = <244144>; /* 8 32k periods */
54 clock-latency-ns = <244144>; /* 8 32k periods */
60 clock-latency-ns = <244144>; /* 8 32k periods */
H A Dsun50i-a64-cpu-opp.dtsi14 clock-latency-ns = <244144>; /* 8 32k periods */
20 clock-latency-ns = <244144>; /* 8 32k periods */
26 clock-latency-ns = <244144>; /* 8 32k periods */
32 clock-latency-ns = <244144>; /* 8 32k periods */
38 clock-latency-ns = <244144>; /* 8 32k periods */
44 clock-latency-ns = <244144>; /* 8 32k periods */
50 clock-latency-ns = <244144>; /* 8 32k periods */
56 clock-latency-ns = <244144>; /* 8 32k periods */
H A Dsun50i-h6-cpu-opp.dtsi12 clock-latency-ns = <244144>; /* 8 32k periods */
21 clock-latency-ns = <244144>; /* 8 32k periods */
30 clock-latency-ns = <244144>; /* 8 32k periods */
39 clock-latency-ns = <244144>; /* 8 32k periods */
48 clock-latency-ns = <244144>; /* 8 32k periods */
57 clock-latency-ns = <244144>; /* 8 32k periods */
66 clock-latency-ns = <244144>; /* 8 32k periods */
75 clock-latency-ns = <244144>; /* 8 32k periods */
84 clock-latency-ns = <244144>; /* 8 32k periods */
93 clock-latency-ns = <244144>; /* 8 32k periods */
H A Dsun50i-a100-cpu-opp.dtsi12 clock-latency-ns = <244144>; /* 8 32k periods */
21 clock-latency-ns = <244144>; /* 8 32k periods */
30 clock-latency-ns = <244144>; /* 8 32k periods */
39 clock-latency-ns = <244144>; /* 8 32k periods */
48 clock-latency-ns = <244144>; /* 8 32k periods */
57 clock-latency-ns = <244144>; /* 8 32k periods */
66 clock-latency-ns = <244144>; /* 8 32k periods */
/linux/fs/btrfs/tests/
H A Dextent-map-tests.c50 * extent [0, 16K), followed by another file extent [16K, 20K), two dio reads
51 * are entering btrfs_get_extent() concurrently, t1 is reading [8K, 16K), t2 is
52 * reading [0, 8K)
57 * -> add_extent_mapping(0, 16K)
59 * ->add_extent_mapping(0, 16K)
77 /* Add [0, 16K) */ in test_case_1()
87 test_err("cannot add extent range [0, 16K)"); in test_case_1()
92 /* Add [16K, 20K) following [0, 16K) */ in test_case_1()
109 test_err("cannot add extent range [16K, 20K)"); in test_case_1()
121 /* Add [0, 8K), should return [0, 16K) instead. */ in test_case_1()
[all …]
/linux/drivers/net/wireless/ath/
H A Dkey.c130 const struct ath_keyval *k, in ath_hw_set_keycache_entry() argument
143 switch (k->kv_type) { in ath_hw_set_keycache_entry()
164 if (k->kv_len < WLAN_KEY_LEN_WEP40) { in ath_hw_set_keycache_entry()
166 k->kv_len); in ath_hw_set_keycache_entry()
169 if (k->kv_len <= WLAN_KEY_LEN_WEP40) in ath_hw_set_keycache_entry()
171 else if (k->kv_len <= WLAN_KEY_LEN_WEP104) in ath_hw_set_keycache_entry()
180 ath_err(common, "cipher %u not supported\n", k->kv_type); in ath_hw_set_keycache_entry()
184 key0 = get_unaligned_le32(k->kv_val + 0); in ath_hw_set_keycache_entry()
185 key1 = get_unaligned_le16(k->kv_val + 4); in ath_hw_set_keycache_entry()
186 key2 = get_unaligned_le32(k->kv_val + 6); in ath_hw_set_keycache_entry()
[all …]
/linux/lib/crypto/x86/
H A Dsha256-avx2-asm.S160 addl \disp(%rsp, SRND), h # h = k + w + h # --
174 add h, d # d = k + w + h + d # --
188 vpslld $(32-7), XTMP1, XTMP3
190 add y1, h # h = k + w + h + S0 # --
192 add y2, d # d = k + w + h + d + S1 + CH = d + t1 # --
196 add y2, h # h = k + w + h + S0 + S1 + CH = t1 + S0# --
208 addl offset(%rsp, SRND), h # h = k + w + h # --
223 add h, d # d = k + w + h + d # --
225 vpslld $(32-18), XTMP1, XTMP1
242 add y1, h # h = k + w + h + S0 # --
[all …]
/linux/drivers/irqchip/
H A Dirq-renesas-intc-irqpin.c35 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
36 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
37 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
38 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
39 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
146 /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */ in intc_irqpin_mask_unmask_prio()
148 int shift = 32 - (irq + 1) * bitfield_width; in intc_irqpin_mask_unmask_prio()
157 /* The SENSE register is assumed to be 32-bit. */ in intc_irqpin_set_sense()
159 int shift = 32 - (irq + 1) * bitfield_width; in intc_irqpin_set_sense()
304 int k; in intc_irqpin_shared_irq_handler() local
[all …]
/linux/tools/include/linux/
H A Djhash.h14 * These are functions for producing 32-bit hashes for hash table lookup.
34 /* __jhash_mix -- mix 3 32-bit values reversibly. */
45 /* __jhash_final - final mixing of 3 32-bit values (a,b,c) into c */
61 * @k: sequence of bytes as key
73 const u8 *k = key; in jhash() local
78 /* All but the last block: affect some 32 bits of (a,b,c) */ in jhash()
80 a += __get_unaligned_cpu32(k); in jhash()
81 b += __get_unaligned_cpu32(k + 4); in jhash()
82 c += __get_unaligned_cpu32(k + 8); in jhash()
85 k += 12; in jhash()
[all …]
/linux/include/linux/
H A Djhash.h14 * These are functions for producing 32-bit hashes for hash table lookup.
34 /* __jhash_mix - mix 3 32-bit values reversibly. */
45 /* __jhash_final - final mixing of 3 32-bit values (a,b,c) into c */
61 * @k: sequence of bytes as key
73 const u8 *k = key; in jhash() local
78 /* All but the last block: affect some 32 bits of (a,b,c) */ in jhash()
80 a += get_unaligned((u32 *)k); in jhash()
81 b += get_unaligned((u32 *)(k + 4)); in jhash()
82 c += get_unaligned((u32 *)(k + 8)); in jhash()
85 k += 12; in jhash()
[all …]
H A Dzconf.h13 that is: 128K for windowBits=15 + 128K for memLevel = 8 (default values)
15 the default memory requirements from 256K to 128K, compile with
20 that is, 32K for windowBits=15 (default value) plus a few kilobytes
35 # define MAX_WBITS 15 /* 32K LZ77 window */
54 typedef unsigned long uLong; /* 32 bits or more */
H A Dzutil.h11 /* @(#) $Id: zutil.h,v 1.1 2000/01/01 03:32:23 davem Exp $ */
55 /* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */
65 Update a running Adler-32 checksum with the bytes buf[0..len-1] and
68 An Adler-32 checksum is almost as reliable as a CRC32 but can be computed
84 int k; in zlib_adler32() local
89 k = len < NMAX ? len : NMAX; in zlib_adler32()
90 len -= k; in zlib_adler32()
91 while (k >= 16) { in zlib_adler32()
94 k -= 16; in zlib_adler32()
96 if (k != 0) do { in zlib_adler32()
[all …]
/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
36 #define HP_400 10 /* 50MHz 68030+32K external cache */
/linux/lib/
H A Dbitmap.c40 unsigned int k, lim = bits/BITS_PER_LONG; in __bitmap_equal() local
41 for (k = 0; k < lim; ++k) in __bitmap_equal()
42 if (bitmap1[k] != bitmap2[k]) in __bitmap_equal()
46 if ((bitmap1[k] ^ bitmap2[k]) & BITMAP_LAST_WORD_MASK(bits)) in __bitmap_equal()
58 unsigned int k, lim = bits / BITS_PER_LONG; in __bitmap_or_equal() local
61 for (k = 0; k < lim; ++k) { in __bitmap_or_equal()
62 if ((bitmap1[k] | bitmap2[k]) != bitmap3[k]) in __bitmap_or_equal()
69 tmp = (bitmap1[k] | bitmap2[k]) ^ bitmap3[k]; in __bitmap_or_equal()
75 unsigned int k, lim = BITS_TO_LONGS(bits); in __bitmap_complement() local
76 for (k = 0; k < lim; ++k) in __bitmap_complement()
[all …]
/linux/crypto/
H A Dwp512.c31 #define WP256_DIGEST_SIZE 32
34 #define WP512_LENGTHBYTES 32
782 u64 K[8]; /* the round key */ in wp512_process_buffer() local
790 state[0] = block[0] ^ (K[0] = wctx->hash[0]); in wp512_process_buffer()
791 state[1] = block[1] ^ (K[1] = wctx->hash[1]); in wp512_process_buffer()
792 state[2] = block[2] ^ (K[2] = wctx->hash[2]); in wp512_process_buffer()
793 state[3] = block[3] ^ (K[3] = wctx->hash[3]); in wp512_process_buffer()
794 state[4] = block[4] ^ (K[4] = wctx->hash[4]); in wp512_process_buffer()
795 state[5] = block[5] ^ (K[5] = wctx->hash[5]); in wp512_process_buffer()
796 state[6] = block[6] ^ (K[6] = wctx->hash[6]); in wp512_process_buffer()
[all …]
/linux/drivers/spi/
H A Dspi-sh-msiof.c148 if (!div_pow && div <= 32 && div > 2) in sh_msiof_spi_set_clk_regs()
156 for (; brps > 32; div_pow++) in sh_msiof_spi_set_clk_regs()
159 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */ in sh_msiof_spi_set_clk_regs()
163 brps = 32; in sh_msiof_spi_set_clk_regs()
302 unsigned int k; in sh_msiof_spi_write_fifo_8() local
304 for (k = 0; k < words; k++) in sh_msiof_spi_write_fifo_8()
305 sh_msiof_write(p, SITFDR, buf_8[k] << fs); in sh_msiof_spi_write_fifo_8()
313 unsigned int k; in sh_msiof_spi_write_fifo_16() local
315 for (k = 0; k < words; k++) in sh_msiof_spi_write_fifo_16()
316 sh_msiof_write(p, SITFDR, buf_16[k] << fs); in sh_msiof_spi_write_fifo_16()
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a33.dtsi56 clock-latency-ns = <244144>; /* 8 32k periods */
62 clock-latency-ns = <244144>; /* 8 32k periods */
68 clock-latency-ns = <244144>; /* 8 32k periods */
74 clock-latency-ns = <244144>; /* 8 32k periods */
80 clock-latency-ns = <244144>; /* 8 32k periods */
86 clock-latency-ns = <244144>; /* 8 32k periods */
92 clock-latency-ns = <244144>; /* 8 32k periods */
98 clock-latency-ns = <244144>; /* 8 32k periods */
104 clock-latency-ns = <244144>; /* 8 32k periods */
110 clock-latency-ns = <244144>; /* 8 32k periods */
[all …]
/linux/drivers/mtd/
H A Dssfdc.c45 1MiB 2MiB 4MiB 8MiB 16MiB 32MiB 64MiB 128MiB
48 NSector 4 8 8 16 16 16 32 32
49 SumSector 2,000 4,000 8,000 16,000 32,000 64,000 128,000 256,000
67 { MiB( 32), 500, 8, 16 },
68 { MiB( 64), 500, 8, 32 },
69 { MiB(128), 500, 16, 32 },
76 int k; in get_chs() local
79 k = 0; in get_chs()
80 while (chs_table[k].size > 0 && size > chs_table[k].size) in get_chs()
81 k++; in get_chs()
[all …]
/linux/arch/m68k/fpsp040/
H A Dsrem_mod.S28 | Step 2. Set L := expo(X)-expo(Y), k := 0, Q := 0.
39 | 3.4 k := k + 1, j := j - 1, Q := 2Q, R := 2R. Go to
129 subil #32,%d3
131 bfffo %d4{#0:#32},%d6
139 bfffo %d4{#0:#32},%d6
145 addil #32,%d6
174 subil #32,%d0
176 bfffo %d1{#0:#32},%d6
184 bfffo %d1{#0:#32},%d6
190 addil #32,%d6
[all …]
/linux/arch/arm64/include/asm/
H A Datomic_ll_sc.h16 #define K macro
106 ATOMIC_OPS(and, and, K) in ATOMIC_OPS()
107 ATOMIC_OPS(or, orr, K) in ATOMIC_OPS()
108 ATOMIC_OPS(xor, eor, K) in ATOMIC_OPS()
253 if (sz < 32) \
275 * handle the 'K' constraint for the value 4294967295 - thus we use no
276 * constraint for 32 bit operations.
278 __CMPXCHG_CASE(w, b, , 8, , , , , K)
279 __CMPXCHG_CASE(w, h, , 16, , , , , K)
280 __CMPXCHG_CASE(w, , , 32, , , , , K)
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
44 /* k is 1 only on these cases */ in sun4i_get_pll1_factors()
47 req->k = 1; in sun4i_get_pll1_factors()
49 req->k = 0; in sun4i_get_pll1_factors()
55 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ in sun4i_get_pll1_factors()
56 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
59 /* p will be 1 for even divs under 32, divs under 40 and odd pairs in sun4i_get_pll1_factors()
68 /* calculate a suitable n based on k and p */ in sun4i_get_pll1_factors()
70 div /= (req->k + 1); in sun4i_get_pll1_factors()
[all …]
/linux/Documentation/crypto/
H A Ddescore-readme.rst35 .. README,v 1.15 1992/05/20 00:25:32 how E
42 2. PORTABILITY to any byte-addressable host with a 32bit unsigned C type
62 - 30us per encryption (options: 64k tables, no IP/FP)
63 - 33us per encryption (options: 64k tables, FIPS standard bit ordering)
64 - 45us per encryption (options: 2k tables, no IP/FP)
65 - 48us per encryption (options: 2k tables, FIPS standard bit ordering)
66 - 275us to set a new key (uses 1k of key tables)
80 - 53us per encryption (uses 2k of tables)
81 - 96us to set a new key (uses 2.25k of key tables)
106 - 68us per encryption (uses 2k of tables)
[all …]
/linux/arch/powerpc/
H A DKconfig18 config 32BIT
37 # 32T of address space (2^45), which should ensure a reasonable gap
39 # consume "normal" amounts of address space. Book3S 64 only supports 64K
40 # and 4K page sizes.
41 default 29 if PPC_BOOK3S_64 && PPC_64K_PAGES # 29 = 45 (32T) - 16 (64K)
42 default 33 if PPC_BOOK3S_64 # 33 = 45 (32T) - 12 (4K)
46 # of address space (2^44). Only 4K page sizes are supported.
47 default 32 if 64BIT # 32 = 44 (16T) - 12 (4K)
49 # For 32-bit, use the compat values, as they're the same.
54 default 14 if 64BIT && PPC_64K_PAGES # 14 = 30 (1GB) - 16 (64K)
[all …]
/linux/drivers/rtc/
H A Drtc-ti-k3.c51 .reg_bits = 32,
52 .val_bits = 32,
110 * @rate_32k: 32k clock rate in Hz
230 /* Enable Shadow register sync on 32k clock boundary */ in k3rtc_configure()
235 * This ensures that the 32k based sync is active. in k3rtc_configure()
243 "Failed fence osc_dep enable(%d) - is 32k clk working?!\n", ret); in k3rtc_configure()
273 rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, tm); in ti_k3_rtc_read_time()
291 regmap_write(priv->regmap, REG_K3RTC_S_CNT_MSW, seconds >> 32); in ti_k3_rtc_set_time()
310 * ISR to fire as we are checking sync (which should be done in a 32k in ti_k3_rtc_alarm_irq_enable()
324 rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, &alarm->time); in ti_k3_rtc_read_alarm()
[all …]

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