Lines Matching +full:32 +full:k
51 .reg_bits = 32,
52 .val_bits = 32,
110 * @rate_32k: 32k clock rate in Hz
230 /* Enable Shadow register sync on 32k clock boundary */ in k3rtc_configure()
235 * This ensures that the 32k based sync is active. in k3rtc_configure()
243 "Failed fence osc_dep enable(%d) - is 32k clk working?!\n", ret); in k3rtc_configure()
273 rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, tm); in ti_k3_rtc_read_time()
291 regmap_write(priv->regmap, REG_K3RTC_S_CNT_MSW, seconds >> 32); in ti_k3_rtc_set_time()
310 * ISR to fire as we are checking sync (which should be done in a 32k in ti_k3_rtc_alarm_irq_enable()
324 rtc_time64_to_tm((((time64_t)seconds_hi) << 32) | (time64_t)seconds_lo, &alarm->time); in ti_k3_rtc_read_alarm()
340 k3rtc_field_write(priv, K3RTC_ALM_S_CNT_MSW, (seconds >> 32)); in ti_k3_rtc_set_alarm()
412 * de-assert depends on 32k clock edge in the 32k domain in ti_k3_rtc_interrupt()
413 * If we clear the status prior to the first 32k clock edge, in ti_k3_rtc_interrupt()
417 * We can either do that by polling the 32k observability signal for in ti_k3_rtc_interrupt()
438 * 32k domain and vbus domain. in ti_k3_rtc_interrupt()
450 * Force the 32k status to be reloaded back in to ensure status is in ti_k3_rtc_interrupt()
526 /* Make sure we are exact 32k clock. Else, try to compensate delay */ in k3rtc_get_32kclk()
532 * Sync timeout should be two 32k clk sync cycles = ~61uS. We double in k3rtc_get_32kclk()