Home
last modified time | relevance | path

Searched +full:32 +full:bit (Results 1 – 25 of 1399) sorted by relevance

12345678910>>...56

/linux/drivers/net/fddi/skfp/h/
H A Dskfbi.h40 #define B0_RAP 0x0000 /* 8 bit register address port */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
47 #define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
52 #define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
53 #define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
54 #define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
[all …]
/linux/include/linux/
H A Dmath64.h16 * div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder
17 * @dividend: unsigned 64bit dividend
18 * @divisor: unsigned 32bit divisor
19 * @remainder: pointer to unsigned 32bit remainder
23 * This is commonly provided by 32bit archs to provide an optimized 64bit
33 * div_s64_rem - signed 64bit divide with 32bit divisor with remainder
34 * @dividend: signed 64bit dividend
35 * @divisor: signed 32bit divisor
36 * @remainder: pointer to signed 32bit remainder
47 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
[all …]
H A Dexportfs.h34 * 32bit inode number, 32 bit generation number.
39 * 32bit inode number, 32 bit generation number,
40 * 32 bit parent directory inode number.
45 * 64 bit object ID, 64 bit root object ID,
46 * 32 bit generation number.
51 * 64 bit object ID, 64 bit root object ID,
52 * 32 bit generation number,
53 * 64 bit parent object ID, 32 bit parent generation.
58 * 64 bit object ID, 64 bit root object ID,
59 * 32 bit generation number,
[all …]
H A Dnfs4.h111 OP_SAVEFH = 32,
438 FATTR4_MIMETYPE = 32,
521 * attribute bits within 32-bit word boundaries.
525 #define FATTR4_WORD0_SUPPORTED_ATTRS BIT(FATTR4_SUPPORTED_ATTRS)
526 #define FATTR4_WORD0_TYPE BIT(FATTR4_TYPE)
527 #define FATTR4_WORD0_FH_EXPIRE_TYPE BIT(FATTR4_FH_EXPIRE_TYPE)
528 #define FATTR4_WORD0_CHANGE BIT(FATTR4_CHANGE)
529 #define FATTR4_WORD0_SIZE BIT(FATTR4_SIZE)
530 #define FATTR4_WORD0_LINK_SUPPORT BIT(FATTR4_LINK_SUPPORT)
531 #define FATTR4_WORD0_SYMLINK_SUPPORT BIT(FATTR4_SYMLINK_SUPPORT)
[all …]
H A Dcrc32.h9 * crc32_le() - Compute least-significant-bit-first IEEE CRC-32
15 * This implements the CRC variant that is often known as the IEEE CRC-32, or
16 * simply CRC-32, and is widely used in Ethernet and other applications:
18 * - Polynomial: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 +
20 * - Bit order: Least-significant-bit-first
26 * For new applications, prefer to use CRC-32C instead. See crc32c().
40 * crc32_be() - Compute most-significant-bit-first IEEE CRC-32
47 * *most-significant-bit-first* variant of the CRC. I.e., within each byte, the
48 * most significant bit is processed first (treated as highest order polynomial
49 * coefficient). The same bit order is also used for the CRC value itself:
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.h131 /* B0_CTST 16 bit Control/Status register */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
168 /* Bit 30: reserved */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
238 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
[all …]
H A Dsky2.h41 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
48 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
49 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
50 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
52 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
53 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
57 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
91 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
94 P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn66xx_regs.h89 /* 1 register (32-bit) to enable Input queues */
92 /* 1 register (32-bit) to enable Output queues */
95 /* 1 register (32-bit) to determine whether Output queues are in reset. */
98 /* 1 register (32-bit) to determine whether Input queues are in reset. */
103 /* 1 register (32-bit) - instr. size of each input queue. */
106 /* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
109 /* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */
112 /* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */
115 /* 32 registers for Input Queue size - SLI_PKT0_INSTR_FIFO_RSIZE */
118 /* 32 registers for Instruction Header Options - SLI_PKT0_INSTR_HEADER */
[all …]
/linux/arch/alpha/kernel/
H A Dsys_sable.c39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
43 void (*ack_irq_hw)(unsigned long bit);
64 * Bit Meaning Kernel IRQ
68 * 2 TULIP (builtin) 32
93 sable_update_irq_hw(unsigned long bit, unsigned long mask) in sable_update_irq_hw() argument
97 if (bit >= 16) { in sable_update_irq_hw()
100 } else if (bit >= 8) { in sable_update_irq_hw()
109 sable_ack_irq_hw(unsigned long bit) in sable_ack_irq_hw() argument
113 if (bit >= 16) { in sable_ack_irq_hw()
[all …]
/linux/drivers/staging/media/ipu3/
H A Dipu3-abi.h15 #define IMGU_DVS_BLOCK_H 32
31 #define IMGU_ABI_AF_MAX_CELLS_PER_SET 32
32 #define IMGU_ABI_AWB_FR_MAX_CELLS_PER_SET 32
46 #define IMGU_PM_CTRL_START BIT(0)
47 #define IMGU_PM_CTRL_CFG_DONE BIT(1)
48 #define IMGU_PM_CTRL_RACE_TO_HALT BIT(2)
49 #define IMGU_PM_CTRL_NACK_ALL BIT(3)
50 #define IMGU_PM_CTRL_CSS_PWRDN BIT(4)
51 #define IMGU_PM_CTRL_RST_AT_EOF BIT(5)
52 #define IMGU_PM_CTRL_FORCE_HALT BIT(6)
[all …]
/linux/lib/
H A Diomap_copy.c10 * __iowrite32_copy - copy data to MMIO space, in 32-bit units
11 * @to: destination, in MMIO space (must be 32-bit aligned)
12 * @from: source (must be 32-bit aligned)
13 * @count: number of 32-bit quantities to copy
15 * Copy data from kernel space to MMIO space, in units of 32 bits at a
33 * __ioread32_copy - copy data from MMIO space, in 32-bit units
34 * @to: destination (must be 32-bit aligned)
35 * @from: source, in MMIO space (must be 32-bit aligned)
36 * @count: number of 32-bit quantities to copy
38 * Copy data from MMIO space to kernel space, in units of 32 bits at a
[all …]
/linux/include/uapi/linux/
H A Dswab.h71 __u32 h = val >> 32; in __fswab64()
72 __u32 l = val & ((1ULL << 32) - 1); in __fswab64()
73 return (((__u64)__fswab32(l)) << 32) | ((__u64)(__fswab32(h))); in __fswab64()
98 * __swab16 - return a byteswapped 16-bit value
111 * __swab32 - return a byteswapped 32-bit value
124 * __swab64 - return a byteswapped 64-bit value
140 #else /* __BITS_PER_LONG == 32 */ in __swab()
146 * __swahw32 - return a word-swapped 32-bit value
157 * __swahb32 - return a high and low byte-swapped 32-bit value
168 * __swab16p - return a byteswapped 16-bit value from a pointer
[all …]
/linux/fs/ext4/
H A Dinode-test.c43 "1901-12-13 Lower bound of 32bit < 0 timestamp, no extra bits"
45 "1969-12-31 Upper bound of 32bit < 0 timestamp, no extra bits"
47 "1970-01-01 Lower bound of 32bit >=0 timestamp, no extra bits"
49 "2038-01-19 Upper bound of 32bit >=0 timestamp, no extra bits"
51 "2038-01-19 Lower bound of 32bit <0 timestamp, lo extra sec bit on"
53 "2106-02-07 Upper bound of 32bit <0 timestamp, lo extra sec bit on"
55 "2106-02-07 Lower bound of 32bit >=0 timestamp, lo extra sec bit on"
57 "2174-02-25 Upper bound of 32bit >=0 timestamp, lo extra sec bit on"
59 "2174-02-25 Lower bound of 32bit <0 timestamp, hi extra sec bit on"
61 "2242-03-16 Upper bound of 32bit <0 timestamp, hi extra sec bit on"
[all …]
/linux/lib/tests/
H A Dffs_kunit.c32 /* Single bit patterns - powers of 2 */
33 {0x00000001, 1, 1, "bit 0 set"},
34 {0x00000002, 2, 2, "bit 1 set"},
35 {0x00000004, 3, 3, "bit 2 set"},
36 {0x00000008, 4, 4, "bit 3 set"},
37 {0x00000010, 5, 5, "bit 4 set"},
38 {0x00000020, 6, 6, "bit 5 set"},
39 {0x00000040, 7, 7, "bit 6 set"},
40 {0x00000080, 8, 8, "bit 7 set"},
41 {0x00000100, 9, 9, "bit 8 set"},
[all …]
/linux/Documentation/staging/
H A Dcrc32.rst17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
30 little-endian; the most significant bit (sometimes used for parity)
34 Just like with ordinary division, you proceed one digit (bit) at a time.
35 Each step of the division you take one more digit (bit) of the dividend
39 and to make the XOR cancel, it's just a copy of bit 32 of the remainder.
42 throw the quotient bit away, but subtract the appropriate multiple of
44 ready to process the next bit.
[all …]
/linux/arch/s390/kernel/
H A Dmodule.c63 case R_390_GOT12: /* 12 bit GOT offset. */ in check_rela()
64 case R_390_GOT16: /* 16 bit GOT offset. */ in check_rela()
65 case R_390_GOT20: /* 20 bit GOT offset. */ in check_rela()
66 case R_390_GOT32: /* 32 bit GOT offset. */ in check_rela()
67 case R_390_GOT64: /* 64 bit GOT offset. */ in check_rela()
68 case R_390_GOTENT: /* 32 bit PC rel. to GOT entry shifted by 1. */ in check_rela()
69 case R_390_GOTPLT12: /* 12 bit offset to jump slot. */ in check_rela()
70 case R_390_GOTPLT16: /* 16 bit offset to jump slot. */ in check_rela()
71 case R_390_GOTPLT20: /* 20 bit offset to jump slot. */ in check_rela()
72 case R_390_GOTPLT32: /* 32 bit offset to jump slot. */ in check_rela()
[all …]
/linux/tools/testing/selftests/powerpc/vphn/
H A Dtest-vphn.c41 "vphn: 1 x 16-bit value",
56 "vphn: 2 x 16-bit values",
72 "vphn: 3 x 16-bit values",
89 "vphn: 4 x 16-bit values",
107 /* Parsing the next 16-bit value out of the next 64-bit input
110 "vphn: 5 x 16-bit values",
129 /* Parse at most 6 x 64-bit input values */
130 "vphn: 24 x 16-bit values",
168 "vphn: 1 x 32
[all...]
/linux/lib/math/
H A Ddiv64.c10 * Generic C version of 64bit/32bit division and modulo, with
11 * 64bit result and 32bit remainder.
13 * The fast case for (n>>32 == 0) is handled inline by do_div().
28 /* Not needed on 64bit architectures */
29 #if BITS_PER_LONG == 32
37 uint32_t high = rem >> 32; in __div64_32()
39 /* Reduce the thing a bit first */ in __div64_32()
43 res = (uint64_t) high << 32; in __div64_32()
44 rem -= (uint64_t) (high*base) << 32; in __div64_32()
88 * div64_u64_rem - unsigned 64bit divide with 64bit divisor and remainder
[all …]
/linux/drivers/acpi/acpica/
H A Dtbfadt.c166 * Bit width field in the GAS is only one byte long, 255 max. in acpi_tb_init_generic_address()
170 if (byte_width > 31) { /* (31*8)=248, (32*8)=256 */ in acpi_tb_init_generic_address()
178 "%s - 32-bit FADT register is too long (%u bytes, %u bits) " in acpi_tb_init_generic_address()
188 * The 64-bit Address field is non-aligned in the byte packed in acpi_tb_init_generic_address()
206 * address32 - 32-bit address of the register
207 * address64 - 64-bit address of the register
209 * RETURN: The resolved 64-bit address
211 * DESCRIPTION: Select between 32-bit and 64-bit versions of addresses within
217 * the 32-bit and 64-bit address fields (FIRMWARE_CTRL/X_FIRMWARE_CTRL and
222 * By default, as per the ACPICA specification, a valid 64-bit address is
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
57 {"H27UCG8T2ETR-BC 64G 3.3V 8-bit",
[all …]
/linux/drivers/eisa/
H A Deisa.ids14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
50 ADI0001 "Lightning Networks 32-Bit EISA Ethernet LAN Adapter"
55 AIM0002 "AUVA OPTi/EISA 32-Bit 486 All-in-One System Board"
86 ALR3023 "ALR 16-bit VGA without Parallel port"
134 BUS4201 "BusTek/BusLogic Bt74xB 32-Bit Bus Master EISA-to-SCSI Host Adapter"
135 BUS4202 "BusTek/BusLogic Bt74xC 32-Bit Bus Master EISA-to-SCSI Host Adapter"
136 BUS6001 "BusTek/BusLogic Bt760 32-Bit Bus Master EISA-to-Ethernet Controller"
137 BUS6301 "BusTek/BusLogic Bt763E EISA 32-Bit 82596-based Ethernet Controller"
155 CNT2000 "900E/950E EISA Bus 32-bit Ethernet LAN Adapter"
[all …]
/linux/arch/arm64/include/asm/
H A Dkgdb.h46 * r0-r30: 64 bit
47 * sp,pc : 64 bit
48 * pstate : 32 bit
51 * f0-f31: 128 bit
52 * fpsr & fpcr: 32 bit
53 * Total: 32 + 2
57 * Architecture Reference Manual that claimed "SPSR_ELx is a 32-bit register".
58 * and, as a result, allocated only 32-bits for the PSTATE in the remote
61 * Unfortunately "is a 32-bit register" has a very special meaning for
62 * system registers. It means that "the upper bits, bits[63:32], are
[all …]
/linux/arch/mips/include/asm/
H A Dmips-gic.h58 BUILD_BUG_ON(sz != 32); \
69 BUILD_BUG_ON(sz != 32); \
95 /* For read-only shared bit-per-interrupt registers */
111 addr += (intr / 32) * sizeof(uint32_t); \
112 val = __raw_readl(addr) >> intr % 32; \
118 /* For read-write shared bit-per-interrupt registers */
128 __raw_writeq(BIT(intr % 64), addr); \
130 addr += (intr / 32) * sizeof(uint32_t); \
131 __raw_writel(BIT(intr % 32), addr); \
151 addr += (intr / 32) * sizeof(uint32_t); \
[all …]
/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_hw.h81 ICP_ACCEL_MASK_CIPHER_SLICE = BIT(0),
82 ICP_ACCEL_MASK_AUTH_SLICE = BIT(1),
83 ICP_ACCEL_MASK_PKE_SLICE = BIT(2),
84 ICP_ACCEL_MASK_COMPRESS_SLICE = BIT(3),
85 ICP_ACCEL_MASK_LZS_SLICE = BIT(4),
86 ICP_ACCEL_MASK_EIA3_SLICE = BIT(5),
87 ICP_ACCEL_MASK_SHA3_SLICE = BIT(6),
91 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
92 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1),
93 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2),
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-fau.h57 * bit will be set. Otherwise the value of the register before
67 * bit will be set. Otherwise the value of the register before
77 * bit will be set. Otherwise the value of the register before
87 * bit will be set. Otherwise the value of the register before
97 * the error bit will be set. Otherwise the value of the
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
[all …]

12345678910>>...56