Lines Matching +full:32 +full:bit
58 BUILD_BUG_ON(sz != 32); \
69 BUILD_BUG_ON(sz != 32); \
95 /* For read-only shared bit-per-interrupt registers */
111 addr += (intr / 32) * sizeof(uint32_t); \
112 val = __raw_readl(addr) >> intr % 32; \
118 /* For read-write shared bit-per-interrupt registers */
128 __raw_writeq(BIT(intr % 64), addr); \
130 addr += (intr / 32) * sizeof(uint32_t); \
131 __raw_writel(BIT(intr % 32), addr); \
151 addr += (intr / 32) * sizeof(uint32_t); \
153 _val &= ~BIT(intr % 32); \
154 _val |= val << (intr % 32); \
167 /* For read-only local bit-per-interrupt registers */
174 /* For read-write local bit-per-interrupt registers */
182 GIC_ACCESSOR_RW(32, 0x000, config)
183 #define GIC_CONFIG_COUNTSTOP BIT(28)
190 GIC_ACCESSOR_RW(32, 0x010, counter_32l)
191 GIC_ACCESSOR_RW(32, 0x014, counter_32h)
211 GIC_ACCESSOR_RW(32, 0x280, wedge)
212 #define GIC_WEDGE_RW BIT(31)
228 GIC_ACCESSOR_RW_INTR_REG(32, 0x500, 0x4, map_pin)
229 #define GIC_MAP_PIN_MAP_TO_PIN BIT(31)
230 #define GIC_MAP_PIN_MAP_TO_NMI BIT(30)
234 GIC_ACCESSOR_RW_INTR_REG(32, 0x2000, 0x20, map_vp)
237 GIC_VX_ACCESSOR_RW(32, 0x000, ctl)
238 #define GIC_VX_CTL_FDC_ROUTABLE BIT(4)
239 #define GIC_VX_CTL_SWINT_ROUTABLE BIT(3)
240 #define GIC_VX_CTL_PERFCNT_ROUTABLE BIT(2)
241 #define GIC_VX_CTL_TIMER_ROUTABLE BIT(1)
242 #define GIC_VX_CTL_EIC BIT(0)
245 GIC_VX_ACCESSOR_RO(32, 0x004, pend)
248 GIC_VX_ACCESSOR_RO(32, 0x008, mask)
251 GIC_VX_ACCESSOR_RW(32, 0x00c, rmask)
254 GIC_VX_ACCESSOR_RW(32, 0x010, smask)
257 GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x040, 0x4, map)
260 GIC_VX_ACCESSOR_RW(32, 0x040, wd_map)
263 GIC_VX_ACCESSOR_RW(32, 0x044, compare_map)
266 GIC_VX_ACCESSOR_RW(32, 0x048, timer_map)
269 GIC_VX_ACCESSOR_RW(32, 0x04c, fdc_map)
272 GIC_VX_ACCESSOR_RW(32, 0x050, perfctr_map)
275 GIC_VX_ACCESSOR_RW(32, 0x054, swint0_map)
278 GIC_VX_ACCESSOR_RW(32, 0x058, swint1_map)
281 GIC_VX_ACCESSOR_RW(32, 0x080, other)
285 GIC_VX_ACCESSOR_RO(32, 0x088, ident)
292 GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x100, 0x4, eic_shadow_set)