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/linux/arch/parisc/include/asm/
H A Dassembly.h26 /* Frame alignment for 32- and 64-bit */
62 #define LDREGM ldd,mb
136 zdep \r, 31-(\sa), 32-(\sa), \t
144 /* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
146 extru \r, 31-(\sa), 32-(\sa), \t
154 /* Extract unsigned for 32- and 64-bit
155 * The extru instruction leaves the most significant 32 bits of the
159 extrd,u \r, 32+(\p), \len, \t
165 /* The depi instruction leaves the most significant 32 bits of the
169 depdi \i, 32+(\p), \len, \t
[all …]
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A Dtlb.json47 … "BriefDescription": "This event counts operations that cause a TLB access to the L1I in 2MB page."
52 …"BriefDescription": "This event counts operations that cause a TLB access to the L1I in 32MB page."
57 …BriefDescription": "This event counts operations that cause a TLB access to the L1I in 512MB page."
82 … "BriefDescription": "This event counts operations that cause a TLB access to the L1D in 2MB page."
87 …"BriefDescription": "This event counts operations that cause a TLB access to the L1D in 32MB page."
92 …BriefDescription": "This event counts operations that cause a TLB access to the L1D in 512MB page."
117 … "BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 2MB page."
122 …"BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 32MB page."
127 …BriefDescription": "This event counts operations that cause a TLB refill of the L1I in 512MB page."
152 … "BriefDescription": "This event counts operations that cause a TLB refill of the L1D in 2MB page."
[all …]
/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Dfq_codel.json17 …]+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
38 …9]+ limit 1000p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
80 …]+ limit 10240p flows 1024 quantum.*target 2ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
101 …-9]+ limit 10240p flows 1024 quantum.*target 5ms interval 5ms memory_limit 32Mb ecn drop_batch 64",
122 …imit 10240p flows 1024 quantum 9000 target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 64",
143 …[0-9]+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb drop_batch 64",
164 …ws 1024 quantum.*target 5ms ce_threshold 1.02s interval 100ms memory_limit 32Mb ecn drop_batch 64",
185 …+ limit 10240p flows 1024 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 100",
206 …9]+ limit 1000p flows 256 quantum.*target 5ms interval 100ms memory_limit 32Mb ecn drop_batch 100",
228 … [0-9]+ limit 1000p flows 256 quantum.*target 5ms interval 100ms memory_limit 32Mb drop_batch 100",
[all …]
/linux/Documentation/admin-guide/cgroup-v1/
H A Dhugetlb.rst34 For a system supporting three hugepage sizes (64k, 32M and 1G), the control
55 hugetlb.32MB.limit_in_bytes
56 hugetlb.32MB.max_usage_in_bytes
57 hugetlb.32MB.numa_stat
58 hugetlb.32MB.usage_in_bytes
59 hugetlb.32MB.failcnt
60 hugetlb.32MB.rsvd.limit_in_bytes
61 hugetlb.32MB.rsvd.max_usage_in_bytes
62 hugetlb.32MB.rsvd.usage_in_bytes
63 hugetlb.32MB.rsvd.failcnt
/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2.h16 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
21 #define CFG_SIZE 0x8000000ull /* 96MB CFG + 32MB DBG*/
22 #define CFG_REGION_SIZE 0xC000000ull /* 192MB */
24 #define STM_FLASH_BASE_ADDR 0x1000007FF4000000ull /* Not 256MB aligned */
25 #define STM_FLASH_ALIGNED_OFF 0x4000000ull /* 256 MB alignment */
26 #define STM_FLASH_SIZE 0x2000000ull /* 32MB */
29 #define SPI_FLASH_SIZE 0x1000000ull /* 16MB */
35 #define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */
38 #define BAR0_RSRVD_SIZE 0x1000000ull /* 16MB */
41 #define SRAM_SIZE 0x3000000ull /* 48MB */
/linux/Documentation/fb/
H A Dmatroxfb.rst50 32 0x112 0x183 0x115 0x18B
65 32 0x118 0x193 0x11B 0x19B
84 example 1600x1200x32bpp can be specified by `video=matroxfb:vesa:0x11C,depth:32`.
91 architectures there are some glitches for 24bpp videomodes. 8, 16 and 32bpp
125 memory usable for on-screen display (i.e. max. 8 MB).
140 transaction terminate with success or retry in 32 PCLK).
162 - 0 -> 2x128Kx32 chips, 2MB onboard, probably sgram
163 - 1 -> 2x128Kx32 chips, 4MB onboard, probably sgram
164 - 2 -> 2x256Kx32 chips, 4MB onboard, probably sgram
165 - 3 -> 2x256Kx32 chips, 8MB onboard, probably sgram
[all …]
H A Dintel810.rst37 - Supports color depths of 8, 16, 24 and 32 bits per pixel
88 select amount of system RAM in MB to allocate for the video memory
90 Recommendation: 1 - 4 MB.
123 select at what offset in MB of the logical memory to allocate the
126 offset (16 MB for a 64 MB aperture, 8 MB for a 32 MB aperture) will
127 avoid XFree86's usage and allows up to 7 MB/15 MB of framebuffer
129 (0 for maximum usage, 31/63 MB for the least amount). Note, an
133 (default = 8 or 16 MB)
195 will use 2 MB of System RAM. MTRR support will be enabled. The refresh rate
/linux/drivers/accel/habanalabs/include/gaudi/
H A Dgaudi.h15 #define SRAM_BAR_SIZE 0x4000000ull /* 64MB */
16 #define CFG_BAR_SIZE 0x8000000ull /* 128MB */
19 #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
22 #define SRAM_SIZE 0x1400000 /* 20MB */
30 #define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */
37 #define GAUDI_MSI_ENTRIES 32
/linux/drivers/eisa/
H A Deisa.ids14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
50 ADI0001 "Lightning Networks 32-Bit EISA Ethernet LAN Adapter"
55 AIM0002 "AUVA OPTi/EISA 32-Bit 486 All-in-One System Board"
134 BUS4201 "BusTek/BusLogic Bt74xB 32-Bit Bus Master EISA-to-SCSI Host Adapter"
135 BUS4202 "BusTek/BusLogic Bt74xC 32-Bit Bus Master EISA-to-SCSI Host Adapter"
136 BUS6001 "BusTek/BusLogic Bt760 32-Bit Bus Master EISA-to-Ethernet Controller"
137 BUS6301 "BusTek/BusLogic Bt763E EISA 32-Bit 82596-based Ethernet Controller"
155 CNT2000 "900E/950E EISA Bus 32-bit Ethernet LAN Adapter"
158 COG9002 "Cogent eMASTER+ EISA XL 32-Bit Burst-mode Ethernet Adapter"
[all …]
/linux/sound/isa/gus/
H A Dgus_io.c17 mb(); in snd_gf1_delay()
36 mb(); in __snd_gf1_ctrl_stop()
38 mb(); in __snd_gf1_ctrl_stop()
40 mb(); in __snd_gf1_ctrl_stop()
42 mb(); in __snd_gf1_ctrl_stop()
50 mb(); in __snd_gf1_write8()
52 mb(); in __snd_gf1_write8()
59 mb(); in __snd_gf1_look8()
67 mb(); in __snd_gf1_write16()
69 mb(); in __snd_gf1_write16()
[all...]
/linux/arch/mips/include/asm/sgi/
H A Dgio.h20 * There is 10MB of GIO address space for GIO64 slot devices
23 * 0 GFX 0x1f000000 - 0x1f3fffff 4MB
24 * 1 EXP0 0x1f400000 - 0x1f5fffff 2MB
25 * 2 EXP1 0x1f600000 - 0x1f9fffff 4MB
29 * - MISC 0x1fb00000 - 0x1fbfffff 1MB
32 * - RESERVED 0x18000000 - 0x1effffff 112MB
37 * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
41 * 32-bit IDs are divided into
44 * 1=GIO Product ID is 32 bits wide.
71 * [*] Device provide 32-bit ID.
/linux/arch/arm64/include/asm/
H A Datomic_ll_sc.h42 #define ATOMIC_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\ argument
55 " " #mb \
63 #define ATOMIC_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint) \ argument
76 " " #mb \
138 #define ATOMIC64_OP_RETURN(name, mb, acq, rel, cl, op, asm_op, constraint)\ argument
151 " " #mb \
159 #define ATOMIC64_FETCH_OP(name, mb, acq, rel, cl, op, asm_op, constraint)\ argument
172 " " #mb \
239 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, acq, rel, cl, constraint) \ argument
253 if (sz < 32) \
[all …]
H A Datomic_lse.h36 #define ATOMIC_FETCH_OP(name, mb, op, asm_op, cl...) \ argument
44 " " #asm_op #mb " %w[i], %w[old], %[v]" \
106 #define ATOMIC_FETCH_OP_AND(name, mb, cl...) \ argument
143 #define ATOMIC64_FETCH_OP(name, mb, op, asm_op, cl...) \ argument
151 " " #asm_op #mb " %[i], %[old], %[v]" \
213 #define ATOMIC64_FETCH_OP_AND(name, mb, cl...) \ argument
248 #define __CMPXCHG_CASE(w, sfx, name, sz, mb, cl...) \ argument
256 " cas" #mb #sfx " %" #w "[old], %" #w "[new], %[v]\n" \
267 __CMPXCHG_CASE(w, , , 32, )
271 __CMPXCHG_CASE(w, , acq_, 32, a, "memory")
[all …]
/linux/drivers/accel/habanalabs/include/goya/
H A Dgoya.h15 #define CFG_BAR_SIZE 0x10000000ull /* 256MB */
19 #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/
22 #define SRAM_SIZE 0x32A0000 /* 50.625MB */
/linux/Documentation/arch/powerpc/
H A Dpci_iov_resource_on_powernv.rst64 the 32-bit space and one much higher) which, via a combination of the
87 32-bit PCIe accesses. We configure that window at boot from FW and
98 the segment granularity is 2GB/256 = 8MB.
112 * Must be at least 256MB in size.
141 update the M32 PE# for the devices that use both 32-bit and 64-bit
142 spaces or assign the remaining PE# to 32-bit only devices.
180 1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.
181 This region is divided into eight contiguous 1MB regions, each of which
183 describes an 8MB region, the alignment requirement is for a single VF,
184 i.e., 1MB in this example.
[all …]
/linux/include/linux/bcma/
H A Dbcma_regs.h76 #define BCMA_SOC_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
78 #define BCMA_SOC_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
80 #define BCMA_SOC_SDRAM_R2 0x80000000U /* Region 2 for sdram (512 MB) */
87 * (2 ZettaBytes), low 32 bits
90 * (2 ZettaBytes), high 32 bits
93 #define BCMA_SOC_PCI1_MEM 0x40000000U /* Host Mode sb2pcitranslation0 (64 MB) */
94 #define BCMA_SOC_PCI1_CFG 0x44000000U /* Host Mode sb2pcitranslation1 (64 MB) */
96 * (2 ZettaBytes), high 32 bits
/linux/tools/perf/pmu-events/arch/arm64/arm/cmn/sys/
H A Dmetric.json42 "MetricExpr": "rnid_rxdat_flits * 32 / 1e6 / duration_time",
43 "ScaleUnit": "1MB/s",
51 "MetricExpr": "rnid_txdat_flits * 32 / 1e6 / duration_time",
52 "ScaleUnit": "1MB/s",
69 "MetricExpr": "sbsx_txdat_flitv * 32 / 1e6 / duration_time",
70 "ScaleUnit": "1MB/s",
/linux/arch/alpha/kernel/
H A Dio.c20 mb(); in ioread8()
22 mb(); in ioread8()
29 mb(); in ioread16()
31 mb(); in ioread16()
38 mb(); in ioread32()
40 mb(); in ioread32()
47 mb(); in ioread64()
49 mb(); in ioread64()
55 mb(); in iowrite8()
61 mb(); in iowrite16()
[all …]
/linux/Documentation/arch/x86/x86_64/
H A Dmm.rst20 from TB to GB and then MB/KB.
59 ffffc90000000000 | -55 TB | ffffe8ffffffffff | 32 TB | vmalloc/ioremap space (vmalloc_base)
77 …ffffffff80000000 | -2 GB | ffffffff9fffffff | 512 MB | kernel text mapping, mapped to physic…
78 ffffffff80000000 |-2048 MB | | |
79 ffffffffa0000000 |-1536 MB | fffffffffeffffff | 1520 MB | module mapping space
80 ffffffffff000000 | -16 MB | | |
81 …FIXADDR_START | ~-11 MB | ffffffffff5fffff | ~0.5 MB | kernel-internal fixmap range, variable s…
82 ffffffffff600000 | -10 MB | ffffffffff600fff | 4 kB | legacy vsyscall ABI
83 ffffffffffe00000 | -2 MB | ffffffffffffffff | 2 MB | ... unused hole
127 …ff11000000000000 | -59.75 PB | ff90ffffffffffff | 32 PB | direct mapping of all physical memory…
[all …]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6.h71 #define IPU6_DEVICE_GDA_VIRT_FACTOR 32
95 #define IPU6_MMU_ADDR_BITS 32
99 #define IPU6_MMU_MAX_TLB_L1_STREAMS 32
100 #define IPU6_MMU_MAX_TLB_L2_STREAMS 32
152 * L2 -> 16 streams and 32 blocks. 2 blocks per streams
153 * One L2 block maps to 1024 L1 entries, hence points to 4MB address range
154 * 2 blocks per L2 stream means, 1 stream points to 8MB range
156 * As we need to clear the caches and 8MB being the biggest cache size, we need
157 * to have trash buffer which points to 8MB address range. As these trash
159 * amount of physical memory. So we reserve 8MB IOVA address range but only
[all …]
/linux/arch/arc/plat-axs10x/
H A Daxs10x.c44 * | snps,dw-apb-intc (MB)| in axs10x_enable_gpio_intc_wire()
55 * DT hardware topology - connect MB intc directly to cpu intc in axs10x_enable_gpio_intc_wire()
94 char mb[32]; in axs10x_early_init() local
104 scnprintf(mb, 32, "MainBoard v%d", mb_rev); in axs10x_early_init()
105 axs10x_print_board_ver(CREG_MB_VER, mb); in axs10x_early_init()
121 * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each
122 * of which maps to a corresponding 256MB aperture in Target slave memory map.
127 * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel:
131 * MB AXI Tunnel Master, which also has a mem map setup
133 * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup
[all …]
/linux/arch/powerpc/boot/dts/
H A Dxcalibur1501.dts33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
46 d-cache-line-size = <32>; // 32 bytes
47 i-cache-line-size = <32>; // 32 bytes
48 d-cache-size = <0x8000>; // L1, 32K
49 i-cache-size = <0x8000>; // L1, 32K
79 reg = <0 0 0x8000000>; /* 128MB */
84 reg = <0x00000000 0x6f00000>; /* 111 MB */
[all …]
/linux/tools/perf/tests/shell/common/
H A Dpatterns.sh44 #! Po úno 14 15:17:32 2010
167 export RE_LINE_RECORD2="^\[\s+perf\s+record:\s+Captured and wrote $RE_NUMBER\s*MB\s+(?:[\w\+\.-]*(?…
170 # [ perf record: Captured and wrote 0.405 MB perf.data (109 samples) ]
171 # [ perf record: Captured and wrote 0.405 MB perf.data (~109 samples) ]
172 # [ perf record: Captured and wrote 0.405 MB /some/temp/dir/perf.data (109 samples) ]
173 # [ perf record: Captured and wrote 0.405 MB ./perf.data (109 samples) ]
174 # [ perf record: Captured and wrote 0.405 MB ./perf.data.3 (109 samples) ]
177 export RE_LINE_RECORD2_TOLERANT="^\[\s+perf\s+record:\s+Captured and wrote $RE_NUMBER\s*MB\s+(?:[\w…
180 # [ perf record: Captured and wrote 0.405 MB perf.data (109 samples) ]
181 # [ perf record: Captured and wrote 0.405 MB perf.data (~109 samples) ]
[all …]
/linux/Documentation/arch/riscv/
H A Dvm-layout.rst13 RISC-V Linux Kernel 32bit
50 ffffffc4fea00000 | -236 GB | ffffffc4feffffff | 6 MB | fixmap
51 ffffffc4ff000000 | -236 GB | ffffffc4ffffffff | 16 MB | PCI io
56 fffffff700000000 | -36 GB | fffffffeffffffff | 32 GB | kasan
87 ffff8d7ffea00000 | -114.5 TB | ffff8d7ffeffffff | 6 MB | fixmap
88 ffff8d7fff000000 | -114.5 TB | ffff8d7fffffffff | 16 MB | PCI io
90 ffff8f8000000000 | -112.5 TB | ffffaf7fffffffff | 32 TB | vmalloc/ioremap space
123 ff1bfffffea00000 | -57 PB | ff1bfffffeffffff | 6 MB | fixmap
124 ff1bffffff000000 | -57 PB | ff1bffffffffffff | 16 MB | PCI io
127 … ff60000000000000 | -40 PB | ffdeffffffffffff | 32 PB | direct mapping of all physical memory
/linux/arch/sh/mm/
H A DKconfig81 def_bool !32BIT
84 config 32BIT
89 bool "Support 32-bit physical addressing through PMB"
91 select 32BIT
95 32-bits through the SH-4A PMB. If this is not set, legacy
173 bool "1MB"
176 bool "4MB"
180 bool "64MB"
199 bool "Enable 32KB cache size for SH7705"

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