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/linux/Documentation/fb/
H A Dviafb.modes14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
30 geometry 640 480 640 480 32
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dlpc1850-creg-clk.txt5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherals to enable low
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 32 kHz Oscillator
H A Dmaxim,max77686.txt1 Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
19 The MAX77686 contains one 32.768khz clock outputs that can be controlled
34 - 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620)
35 - 1: 32khz_cp clock (max77686, max77802),
36 - 2: 32khz_pmic clock (max77686).
H A Dclk-palmas-clk32kg-clocks.txt1 * Palmas 32KHz clocks *
3 Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
/linux/drivers/video/fbdev/core/
H A Dmodedb.c38 /* 640x400 @ 70 Hz, 31.5 kHz hsync */
42 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
43 { NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2, 0,
46 /* 800x600 @ 56 Hz, 35.15 kHz hsync */
50 /* 1024x768 @ 87 Hz interlaced, 35.5 kHz hsync */
54 /* 640x400 @ 85 Hz, 37.86 kHz hsync */
55 { NULL, 85, 640, 400, 31746, 96, 32, 41, 1, 64, 3,
58 /* 640x480 @ 72 Hz, 36.5 kHz hsync */
62 /* 640x480 @ 75 Hz, 37.50 kHz hsync */
66 /* 800x600 @ 60 Hz, 37.8 kHz hsync */
[all …]
/linux/arch/arm/mach-omap1/
H A Dtimer32k.c4 * OMAP 32K Timer
59 * 32KHz OS timer
62 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
63 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
65 * with the 32KHz synchronized timer.
129 .name = "32k-timer",
152 IRQF_TIMER | IRQF_IRQPOLL, "32KHz timer", NULL)) in omap_init_32k_timer()
153 pr_err("Failed to request irq %d(32KHz timer)\n", INT_OS_TIMER); in omap_init_32k_timer()
160 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
167 * 32KHz clocksource ... always available, on pretty most chips except
[all …]
H A DKconfig66 bool "Use 32KHz timer"
70 Select this option if you want to enable the OMAP 32KHz timer.
72 support for no tick during idle. The 32KHz timer provides less
73 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
86 timer provides more intra-tick resolution than the 32KHz timer,
/linux/include/sound/
H A Demu10k1.h28 #define MAXPAGES0 4096 /* 32 bit mode */
35 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
209 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
210 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
597 // 32 cache registers (== 128 bytes) per channel follow.
608 // The engine has a fetch threshold of 32 bytes, so it tries to keep
610 // 32 (8-bit mono). The actual transfers are pretty unpredictable,
638 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
639 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
640 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
[all …]
H A Dasoundef.h27 #define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */
28 #define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */
29 #define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */
114 #define IEC958_AES3_CON_FS_44100 (0<<0) /* 44.1kHz */
116 #define IEC958_AES3_CON_FS_48000 (2<<0) /* 48kHz */
117 #define IEC958_AES3_CON_FS_32000 (3<<0) /* 32kHz */
118 #define IEC958_AES3_CON_FS_22050 (4<<0) /* 22.05kHz */
119 #define IEC958_AES3_CON_FS_384000 (5<<0) /* 384kHz */
120 #define IEC958_AES3_CON_FS_24000 (6<<0) /* 24kHz */
121 #define IEC958_AES3_CON_FS_88200 (8<<0) /* 88.2kHz */
[all …]
H A Ddesignware_i2s.h15 * @data_width: number of bits per sample (8/16/24/32 bit)
16 * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz)
/linux/Documentation/arch/arm/sunxi/
H A Dclocks.rst18 24MHz 32kHz
26 When you are about to suspend, you switch the CPU Mux to the 32kHz
29 24Mhz 32kHz
39 32kHz
/linux/sound/ppc/
H A Dawacs.h112 #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
113 #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
114 #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
115 #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
116 #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */
117 #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */
118 #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */
119 #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
172 #define RATE_48000 (0x0 << 8) /* 48 kHz */
173 #define RATE_44100 (0x0 << 8) /* 44.1 kHz */
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dmax77620.txt36 with internal regulators. 32KHz clock can be programmed to be part of a
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
58 and 32KHz clock get disabled at
68 regulators, GPIOs and 32kHz clocks are provided in their respective
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_defs.h144 /* macro to extract a single byte from 4-byte(32-bit) data */
149 #define MXL_GET_REG_MASK_32(lsb_loc, num_of_bits) ((0xFFFFFFFF >> (32 - (num_of_bits))) << (lsb_loc…
396 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
397 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
398 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
399 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
404 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
[all …]
/linux/arch/mips/alchemy/common/
H A Dtime.c16 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
32 /* 32kHz clock enabled and detected */
43 .mask = CLOCKSOURCE_MASK(32),
82 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock in alchemy_time_init()
86 * (the 32S bit seems to be stuck set to 1 once a single clock- in alchemy_time_init()
101 alchemy_wrsys(0, AU1000_SYS_RTCTRIM); /* 32.768 kHz */ in alchemy_time_init()
119 cd->shift = 32; in alchemy_time_init()
/linux/drivers/cpufreq/
H A Dgx-suspmod.c28 * 32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF)
90 #define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */
128 * (32us * MAX_DURATION). If no parameter is given, this defaults
132 * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */
217 static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, in gx_validate_speed() argument
229 tmp_off = ((khz * i) / stock_freq) & 0xff; in gx_validate_speed()
232 /* if this relation is closer to khz, use this. If it's equal, in gx_validate_speed()
234 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) { in gx_validate_speed()
247 * set cpu speed in khz.
250 static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz) in gx_set_cpuspeed() argument
[all …]
H A Dtegra194-cpufreq.c21 #define KHZ 1000 macro
23 #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
95 opp = dev_pm_opp_find_freq_exact(dev, freq_khz * KHZ, true); in tegra_cpufreq_set_bw()
146 * [63:32] PLLP counter: Counts at fixed frequency (408 MHz)
225 * [63:32] Core clock counter: counts on every core clock cycle
240 return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); in map_ndiv_to_freq()
281 * ref_clk_counter(32 bit counter) runs on constant clk, in tegra_read_counters()
283 * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter in tegra_read_counters()
286 * Like wise core_clk_counter(32 bit counter) runs on core clock. in tegra_read_counters()
289 * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter in tegra_read_counters()
[all …]
/linux/sound/pci/ca0106/
H A Dca0106.h144 * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
203 * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
232 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
233 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
234 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
335 …ne ROUTING1_REAR 0x77000000 /* Channel_id 0 sends to 10, Channel_id 1 sends to 32 */
407 /* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 = 1.0
416 * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
417 * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
419 * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
[all …]
/linux/drivers/media/tuners/
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
41 1a d0 set frequency: 125 kHz scale, n*125 kHz
65 #define QT1010_STEP (125 * kHz) /*
/linux/Documentation/ABI/testing/
H A Dsysfs-class-rtc-rtc0-device-rtc_calibration7 calibrate the AB8500.s 32KHz Real Time Clock.
12 30.5 micro-seconds (half-parts-per-million of the 32KHz clock)
/linux/arch/arm/mach-rockchip/
H A Dpm.c75 * function of usb wakeup, so do not switch to 32khz, since the usb phy in rk3288_slp_disable_osc()
76 * clk does not connect to 32khz osc in rk3288_slp_disable_osc()
142 * switch its main clock supply to the alternative 32kHz in rk3288_slp_mode_set()
143 * source. Therefore set 30ms on a 32kHz clock for pmic in rk3288_slp_mode_set()
147 regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30); in rk3288_slp_mode_set()
151 osc_disable ? 32 * 30 : 0); in rk3288_slp_mode_set()
/linux/drivers/clocksource/
H A Dtimer-ep93xx.c27 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
28 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
31 * The 508 kHz timers are ideal for use for the timer interrupt, as the
32 * most common values of HZ divide 508 kHz nicely. We pick the 32 bit
91 /* Default mode: periodic, off, 508 kHz */ in ep93xx_clkevt_set_next_event()
/linux/Documentation/hwmon/
H A Dg760a.rst24 cycle counts of an assumed 32kHz clock source.
30 from the measured speed pulse period by assuming again a 32kHz clock
/linux/Documentation/sound/cards/
H A Dhdspm.rst37 * Double Speed -- 1..32 channels
42 over the MADI, but all 32 channels are available for the mixer,
54 * Format -- signed 32 Bit Little Endian (SNDRV_PCM_FMTBIT_S32_LE)
143 * Values -- "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
144 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
145 "Internal 96.0 kHz"
/linux/drivers/media/pci/cx23885/
H A Dcx23885-input.c160 /* RC-5: 2,222,222 ns = 1/36 kHz * 32 cycles * 2 marks * 1.25*/ in cx23885_input_ir_start()
161 /* RC-6A: 3,333,333 ns = 1/36 kHz * 16 cycles * 6 marks * 1.25*/ in cx23885_input_ir_start()
163 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */ in cx23885_input_ir_start()
164 /* RC-6A: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */ in cx23885_input_ir_start()
187 params.carrier_freq = 37917; /* Hz, 455 kHz/12 for NEC */ in cx23885_input_ir_start()
193 * NEC max pulse width: (64/3)/(455 kHz/12) * 16 nec_units in cx23885_input_ir_start()
194 * (64/3)/(455 kHz/12) * 16 nec_units * 1.375 = 12378022 ns in cx23885_input_ir_start()
199 * NEC noise filter min width: (64/3)/(455 kHz/12) * 1 nec_unit in cx23885_input_ir_start()
200 * (64/3)/(455 kHz/12) * 1 nec_units * 0.625 = 351648 ns in cx23885_input_ir_start()

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