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/linux/Documentation/fb/
H A Dintel810.rst41 - Full and optimized hardware acceleration at 8, 16 and 24 bpp
93 f. "bpp:<value>"
106 (default = 29/30)
168 than 8 bpp. Useful for color tuning, such as gamma control.
173 o. <xres>x<yres>[-<bpp>][@<refresh>]
191 append="video=i810fb:vram:2,xres:1024,yres:768,bpp:8,hsync1:30,hsync2:55, \
194 This will initialize the framebuffer to 1024x768 at 8bpp. The framebuffer
219 modprobe i810fb vram=2 xres=1024 bpp=8 hsync1=30 hsync2=55 vsync1=50 \
224 options i810fb vram=2 xres=1024 bpp=16 hsync1=30 hsync2=55 vsync1=50 \
/linux/drivers/gpu/drm/tests/
H A Ddrm_dp_mst_helper_test.c17 const int bpp; member
25 .bpp = 30,
31 .bpp = 30,
37 .bpp = 24,
43 .bpp = 24,
49 .bpp = 24,
59 KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp << 4), in drm_test_dp_mst_calc_pbn_mode()
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()
120 .expected = fp_init(30, 22187),
145 .expected = fp_init(30, 0),
/linux/drivers/gpu/drm/msm/dp/
H A Ddp_panel.c94 const u32 max_supported_bpp = 30, min_supported_bpp = 18; in msm_dp_panel_get_supported_bpp()
95 u32 bpp, data_rate_khz; in msm_dp_panel_get_supported_bpp() local
97 bpp = min(mode_edid_bpp, max_supported_bpp); in msm_dp_panel_get_supported_bpp()
103 if (mode_pclk_khz * bpp <= data_rate_khz) in msm_dp_panel_get_supported_bpp()
104 return bpp; in msm_dp_panel_get_supported_bpp()
105 bpp -= 6; in msm_dp_panel_get_supported_bpp()
106 } while (bpp > min_supported_bpp); in msm_dp_panel_get_supported_bpp()
179 u32 bpp; in msm_dp_panel_get_mode_bpp() local
189 bpp = msm_dp_link_bit_depth_to_bpp( in msm_dp_panel_get_mode_bpp()
192 bpp = msm_dp_panel_get_supported_bpp(msm_dp_panel, mode_edid_bpp, in msm_dp_panel_get_mode_bpp()
[all …]
H A Ddp_ctrl.c24 #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
49 int bpp; /* bits */ member
61 u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */
62 u8 bpp; member
153 ctrl->panel->msm_dp_mode.bpp); in msm_dp_ctrl_config_ctrl()
186 ctrl->panel->msm_dp_mode.bpp); in msm_dp_ctrl_configure_source_params()
205 int bpp; member
336 tu->bpp = in->bpp; in msm_dp_panel_update_tu_timings()
352 switch (tu->bpp) { in msm_dp_panel_update_tu_timings()
354 tu->bpp = 16; in msm_dp_panel_update_tu_timings()
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/linux/drivers/staging/sm750fb/
H A Dsm750_accel.h44 #define DE_CONTROL_PATTERN BIT(30)
113 #define DE_STRETCH_FORMAT_PATTERN_XY BIT(30)
193 u32 base, u32 pitch, u32 Bpp,
205 * @Bpp: Color depth of destination surface
216 unsigned int Bpp, unsigned int dx, unsigned int dy,
/linux/drivers/video/fbdev/
H A Datafb.c125 short bpp; member
224 14, 142, 78, 206, 46, 174, 110, 238, 30, 158, 94, 222, 62, 190, 126, 254,
479 "tt-low", 60, 320, 480, 31041, 120, 100, 8, 16, 140, 30,
483 "tt-mid", 60, 640, 480, 31041, 120, 100, 8, 16, 140, 30,
583 int bpp = var->bits_per_pixel; in tt_decode_var() local
588 if (bpp > 1 || xres > sttt_xres * 2 || yres > tt_yres * 2) in tt_decode_var()
593 bpp = 1; in tt_decode_var()
595 if (bpp > 8 || xres > sttt_xres || yres > tt_yres) in tt_decode_var()
597 if (bpp > 4) { in tt_decode_var()
603 bpp = 8; in tt_decode_var()
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H A Dau1200fb.c312 /* Need VGA 640 @ 24bpp, @ 32bpp */
313 /* Need VGA 800 @ 24bpp, @ 32bpp */
314 /* Need VGA 1024 @ 24bpp, @ 32bpp */
1097 /* 16bpp True color. in au1200fb_fb_check_var()
1110 /* 32bpp True color. in au1200fb_fb_check_var()
1257 // limit brightness pwm duty to >= 30/1600 in set_global()
1258 if (pdata->brightness < 30) { in set_global()
1259 pdata->brightness = 30; in set_global()
1296 unsigned int val, bpp; in set_window() local
1320 val |= ((pdata->priority << 30) & LCD_WINCTRL1_PRI); in set_window()
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H A Dimxfb.c46 unsigned char bpp; member
69 #define CPOS_CC0 BIT(30)
83 #define PCR_COLOR BIT(30)
390 var->bits_per_pixel = imxfb_mode->bpp; in imxfb_check_var()
748 u32 bpp; in imxfb_of_read_mode() local
761 ret = of_property_read_u32(np, "bits-per-pixel", &bpp); in imxfb_of_read_mode()
765 dev_err(dev, "Failed to read bpp and pcr from DT\n"); in imxfb_of_read_mode()
769 if (bpp < 1 || bpp > 255) { in imxfb_of_read_mode()
774 imxfb_mode->bpp = bpp; in imxfb_of_read_mode()
940 * be the same as m->bpp/8 in imxfb_probe()
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H A Dtdfxfb.c26 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
96 /* "640x480, 8 bpp @ 60 Hz */
277 * Set the color of a palette entry in 8bpp mode
711 reg.miscinit0 &= ~(1 << 30); in tdfxfb_set_par()
715 reg.miscinit0 |= (1 << 30); in tdfxfb_set_par()
719 reg.miscinit0 |= (1 << 30); in tdfxfb_set_par()
848 u32 bpp = info->var.bits_per_pixel; in tdfxfb_fillrect() local
850 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); in tdfxfb_fillrect()
868 dstbase += dx * bpp >> 3; in tdfxfb_fillrect()
892 u32 bpp = info->var.bits_per_pixel; in tdfxfb_copyarea() local
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H A Dstifb.c42 * - 1bpp mode is completely untested
50 * #define FALLBACK_TO_1BPP to fall back to 1 bpp, or
170 printk(KERN_DEBUG "%30s: WRITE_BYTE(0x%06x) = 0x%02x (old=0x%02x)\n", \
174 printk(KERN_DEBUG "%30s: WRITE_WORD(0x%06x) = 0x%08x (old=0x%08x)\n", \
1194 int bpp, xres, yres; in stifb_init_fb() local
1241 /* default to 8 bpp on most graphic chips */ in stifb_init_fb()
1242 bpp = 8; in stifb_init_fb()
1276 bpp = 32; in stifb_init_fb()
1289 bpp = bpp_pref; in stifb_init_fb()
1291 bpp = 32; in stifb_init_fb()
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/linux/drivers/video/fbdev/core/
H A Dmodedb.c59 { NULL, 72, 640, 480, 31746, 144, 40, 30, 8, 40, 3, 0,
108 { NULL, 100, 800, 600, 14357, 160, 64, 30, 4, 64, 6, 0,
189 { NULL, 60, 1680, 1050, 6848, 280, 104, 30, 3, 176, 6,
407 /* 30 1856x1392-60 VESA */
514 { 0x41, 0xc940, 0x000000, &vesa_modes[30] },
539 * @bpp: color depth in bits per pixel
548 const struct fb_videomode *mode, unsigned int bpp) in fb_try_mode() argument
554 mode->xres, mode->yres, bpp, mode->refresh); in fb_try_mode()
561 var->bits_per_pixel = bpp; in fb_try_mode()
595 * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][p][m]
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/linux/fs/xfs/
H A Dxfs_buf.h50 #define XBF_TRYLOCK (1u << 30)/* lock requested, but do not wait */
227 int nmaps, xfs_buf_flags_t flags, struct xfs_buf **bpp);
229 int nmaps, xfs_buf_flags_t flags, struct xfs_buf **bpp,
241 struct xfs_buf **bpp) in xfs_buf_incore() argument
245 return xfs_buf_get_map(target, &map, 1, XBF_INCORE | flags, bpp); in xfs_buf_incore()
253 struct xfs_buf **bpp) in xfs_buf_get() argument
257 return xfs_buf_get_map(target, &map, 1, 0, bpp); in xfs_buf_get()
266 struct xfs_buf **bpp, in xfs_buf_read() argument
271 return xfs_buf_read_map(target, &map, 1, flags, bpp, ops, in xfs_buf_read()
287 xfs_buf_flags_t flags, struct xfs_buf **bpp);
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/linux/drivers/media/i2c/
H A Dar0521.c284 int bpp; in ar0521_calc_pll() local
302 * - vt_pix = bpp / 2 in ar0521_calc_pll()
304 * - SERIAL_CLOCK = MIPI data rate (Mbps / lane) = WORD_CLOCK * bpp in ar0521_calc_pll()
312 * VCO = PIXEL_CLOCK * bpp / 2 in ar0521_calc_pll()
315 * MIPI_CLK = PIXEL_CLOCK * bpp / 2 / 2 in ar0521_calc_pll()
318 * MIPI_CLK = V4L2_CID_PIXEL_RATE * bpp / lanes / 2 in ar0521_calc_pll()
333 bpp = ar0521_code_to_bpp(sensor); in ar0521_calc_pll()
334 sensor->pll.vt_pix = bpp / 2; in ar0521_calc_pll()
347 /* 0x300 */ be(sensor->pll.vt_pix), /* vt_pix_clk_div = bpp / 2 */ in ar0521_pll_config()
689 be(0x0000), /* 30D2: CRM/CC: enable crm on Visible and CC rows */
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/linux/drivers/gpu/drm/renesas/rz-du/
H A Drzg2l_mipi_dsi.c211 usleep_range(20, 30); in rzg2l_mipi_dsi_dphy_init()
262 unsigned int bpp; in rzg2l_mipi_dsi_startup() local
274 * vclk * bpp = hsclk * 8 * lanes in rzg2l_mipi_dsi_startup()
276 * bpp: video pixel bit depth in rzg2l_mipi_dsi_startup()
282 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in rzg2l_mipi_dsi_startup()
283 hsfreq = (mode->clock * bpp * 8) / (8 * dsi->lanes); in rzg2l_mipi_dsi_startup()
303 * - bpp: maximum 24bpp in rzg2l_mipi_dsi_startup()
400 * 74.25MHz is videoclock of HD@60p or FHD@30p in rzg2l_mipi_dsi_set_display_timing()
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-ldb.yaml19 For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
27 For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h334 # define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30
335 # define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
338 # define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30
339 # define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
358 # define SCALER_DISPCTRLX_RESET BIT(30)
367 /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
396 # define SCALER_DISPBKGND_INTERLACE BIT(30)
407 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
408 # define SCALER_DISPSTATX_MODE_SHIFT 30
473 # define SCALER_GAMADDR_SRAMENB BIT(30)
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/linux/drivers/video/fbdev/sis/
H A Dsis_accel.h134 bit 30 3D engine: 1 is idle,
180 #define SiS300SetupDSTColorDepth(bpp) \ argument
182 MMIO_OUT16(ivideo->mmio_vbase, BR(1)+2, bpp);\
259 bit 30 = 1: Hardware Queue (=HW CQ, 2D queue, 3D queue) empty
310 #define SiS310SetupDSTColorDepth(bpp) \ argument
312 MMIO_OUT16(ivideo->mmio_vbase, AGP_BASE, bpp);\
/linux/drivers/media/v4l2-core/
H A Dv4l2-common.c238 …24, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 3, 0, 0, 0 }, .… in v4l2_format_info()
239 …24, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 3, 0, 0, 0 }, .… in v4l2_format_info()
240 …24, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 3, 0, 0, 0 }, .… in v4l2_format_info()
241 …32, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .… in v4l2_format_info()
242 …R32, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .… in v4l2_format_info()
243 …X32, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .… in v4l2_format_info()
244 …32, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .… in v4l2_format_info()
245 …B32, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .… in v4l2_format_info()
246 …X32, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .… in v4l2_format_info()
247 …32, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 4, 0, 0, 0 }, .… in v4l2_format_info()
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/linux/arch/sparc/include/uapi/asm/
H A Dfbio.h141 #define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
176 int mdi_mode; /* 8bpp, 16bpp or 32bpp */
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h413 # define LC_GO_TO_RECOVERY (1 << 30)
670 #define TRAIN_DONE_D0 (1 << 30)
990 # define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
993 # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
998 # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
1004 # define FMT_75FRC_SEL(x) ((x) << 30)
1032 #define CPG_BUSY (1 << 30)
1057 #define CB_BUSY (1 << 30)
1072 #define SE_DB_BUSY (1 << 30)
1096 #define MEC_ME1_HALT (1 << 30)
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dcikd.h86 /* 8 BPP */
88 /* 16 BPP */
95 /* 32 BPP */
210 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
214 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
223 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
274 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
396 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
451 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c200 /* PPS 30, 31 */ in drm_dsc_pps_payload_pack()
321 * For 6bpp, RC Buffer threshold 12 and 13 need a different value in drm_dsc_set_rc_buf_thresh()
343 u8 bpp; member
348 #define DSC_BPP(bpp) ((bpp) << 4) argument
352 * to DSC 1.1 fractional bpp underflow SCR (DSC_v1.1_E1.pdf)
358 .bpp = DSC_BPP(6), .bpc = 8,
368 .bpp = DSC_BPP(8), .bpc = 8,
378 .bpp = DSC_BPP(8), .bpc = 10,
392 .bpp = DSC_BPP(8), .bpc = 12,
403 .bpp = DSC_BPP(10), .bpc = 8,
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/linux/arch/arm/mach-pxa/
H A Dam200epd.c49 .bpp = 16,
63 .bpp = 16,
66 .right_margin = 30,
77 .bpp = 16,
249 /* we divide since we told the LCD controller we're 16bpp */ in am200_presetup_fb()
/linux/drivers/video/fbdev/aty/
H A Dmach64_gx.c34 #define MAX_M 30
81 const union aty_pll *pll, u32 bpp, u32 accel) in aty_set_dac_514() argument
92 0, 0x41, 0x03, 0x71, 0x45}, /* 8 bpp */ in aty_set_dac_514()
100 switch (bpp) { in aty_set_dac_514()
119 /* Misc Control 2 / 16 BPP Control / 32 BPP Control */ in aty_set_dac_514()
124 u32 bpp, union aty_pll *pll) in aty_var_to_pll_514() argument
206 const union aty_pll *pll, u32 bpp, in aty_set_dac_ATI68860_B() argument
215 switch (bpp) { in aty_set_dac_ATI68860_B()
289 const union aty_pll *pll, u32 bpp, in aty_set_dac_ATT21C498() argument
299 switch (bpp) { in aty_set_dac_ATT21C498()
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/linux/drivers/gpu/drm/gma500/
H A Dintel_bios.c55 dev_priv->edp.bpp = 18; in parse_edp()
59 dev_priv->edp.bpp); in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
102 DRM_DEBUG_KMS("VBT reports EDP: Lane_count %d, Lane_rate %d, Bpp %d\n", in parse_edp()
103 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()

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