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/linux/Documentation/fb/
H A Dintel810.rst41 - Full and optimized hardware acceleration at 8, 16 and 24 bpp
93 f. "bpp:<value>"
106 (default = 29/30)
168 than 8 bpp. Useful for color tuning, such as gamma control.
173 o. <xres>x<yres>[-<bpp>][@<refresh>]
191 append="video=i810fb:vram:2,xres:1024,yres:768,bpp:8,hsync1:30,hsync2:55, \
194 This will initialize the framebuffer to 1024x768 at 8bpp. The framebuffer
219 modprobe i810fb vram=2 xres=1024 bpp=8 hsync1=30 hsync2=55 vsync1=50 \
224 options i810fb vram=2 xres=1024 bpp=16 hsync1=30 hsync2=55 vsync1=50 \
/linux/drivers/gpu/drm/tests/
H A Ddrm_dp_mst_helper_test.c17 const int bpp; member
25 .bpp = 30,
31 .bpp = 30,
37 .bpp = 24,
43 .bpp = 24,
49 .bpp = 24,
59 KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp << 4), in drm_test_dp_mst_calc_pbn_mode()
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()
120 .expected = fp_init(30, 22187),
145 .expected = fp_init(30, 0),
/linux/drivers/staging/sm750fb/
H A Dsm750_accel.h44 #define DE_CONTROL_PATTERN BIT(30)
113 #define DE_STRETCH_FORMAT_PATTERN_XY BIT(30)
193 u32 base, u32 pitch, u32 Bpp,
205 * @Bpp: Color depth of destination surface
216 unsigned int Bpp, unsigned int dx, unsigned int dy,
/linux/drivers/video/fbdev/
H A Datafb.c125 short bpp; member
224 14, 142, 78, 206, 46, 174, 110, 238, 30, 158, 94, 222, 62, 190, 126, 254,
479 "tt-low", 60, 320, 480, 31041, 120, 100, 8, 16, 140, 30,
483 "tt-mid", 60, 640, 480, 31041, 120, 100, 8, 16, 140, 30,
583 int bpp = var->bits_per_pixel; in tt_decode_var() local
588 if (bpp > 1 || xres > sttt_xres * 2 || yres > tt_yres * 2) in tt_decode_var()
593 bpp = 1; in tt_decode_var()
595 if (bpp > 8 || xres > sttt_xres || yres > tt_yres) in tt_decode_var()
597 if (bpp > 4) { in tt_decode_var()
603 bpp = 8; in tt_decode_var()
[all …]
H A Dau1200fb.c312 /* Need VGA 640 @ 24bpp, @ 32bpp */
313 /* Need VGA 800 @ 24bpp, @ 32bpp */
314 /* Need VGA 1024 @ 24bpp, @ 32bpp */
1097 /* 16bpp True color. in au1200fb_fb_check_var()
1110 /* 32bpp True color. in au1200fb_fb_check_var()
1257 // limit brightness pwm duty to >= 30/1600 in set_global()
1258 if (pdata->brightness < 30) { in set_global()
1259 pdata->brightness = 30; in set_global()
1296 unsigned int val, bpp; in set_window() local
1320 val |= ((pdata->priority << 30) & LCD_WINCTRL1_PRI); in set_window()
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H A Dimxfb.c46 unsigned char bpp; member
69 #define CPOS_CC0 BIT(30)
83 #define PCR_COLOR BIT(30)
390 var->bits_per_pixel = imxfb_mode->bpp; in imxfb_check_var()
748 u32 bpp; in imxfb_of_read_mode() local
761 ret = of_property_read_u32(np, "bits-per-pixel", &bpp); in imxfb_of_read_mode()
765 dev_err(dev, "Failed to read bpp and pcr from DT\n"); in imxfb_of_read_mode()
769 if (bpp < 1 || bpp > 255) { in imxfb_of_read_mode()
774 imxfb_mode->bpp = bpp; in imxfb_of_read_mode()
940 * be the same as m->bpp/8 in imxfb_probe()
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H A Dtdfxfb.c26 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
96 /* "640x480, 8 bpp @ 60 Hz */
277 * Set the color of a palette entry in 8bpp mode
711 reg.miscinit0 &= ~(1 << 30); in tdfxfb_set_par()
715 reg.miscinit0 |= (1 << 30); in tdfxfb_set_par()
719 reg.miscinit0 |= (1 << 30); in tdfxfb_set_par()
848 u32 bpp = info->var.bits_per_pixel; in tdfxfb_fillrect() local
850 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); in tdfxfb_fillrect()
868 dstbase += dx * bpp >> 3; in tdfxfb_fillrect()
892 u32 bpp = info->var.bits_per_pixel; in tdfxfb_copyarea() local
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H A Dstifb.c42 * - 1bpp mode is completely untested
50 * #define FALLBACK_TO_1BPP to fall back to 1 bpp, or
170 printk(KERN_DEBUG "%30s: WRITE_BYTE(0x%06x) = 0x%02x (old=0x%02x)\n", \
174 printk(KERN_DEBUG "%30s: WRITE_WORD(0x%06x) = 0x%08x (old=0x%08x)\n", \
1194 int bpp, xres, yres; in stifb_init_fb() local
1241 /* default to 8 bpp on most graphic chips */ in stifb_init_fb()
1242 bpp = 8; in stifb_init_fb()
1276 bpp = 32; in stifb_init_fb()
1289 bpp = bpp_pref; in stifb_init_fb()
1291 bpp = 32; in stifb_init_fb()
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H A Dimsttfb.c79 RRCIV = 30, /* 0x78 */
122 PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */
476 MHz = 30 /* .25 */ ; in compute_imstt_regvals_ibm()
562 set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp) in set_imstt_regvals_ibm() argument
565 __u8 pformat = (bpp >> 3) + 2; in set_imstt_regvals_ibm()
582 set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp) in set_imstt_regvals_tvp() argument
588 switch (bpp) { in set_imstt_regvals_tvp()
654 set_imstt_regvals (struct fb_info *info, u_int bpp) in set_imstt_regvals() argument
661 set_imstt_regvals_ibm(par, bpp); in set_imstt_regvals()
663 set_imstt_regvals_tvp(par, bpp); in set_imstt_regvals()
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/linux/fs/xfs/
H A Dxfs_buf.h50 #define XBF_TRYLOCK (1u << 30)/* lock requested, but do not wait */
217 int nmaps, xfs_buf_flags_t flags, struct xfs_buf **bpp);
219 int nmaps, xfs_buf_flags_t flags, struct xfs_buf **bpp,
231 struct xfs_buf **bpp) in xfs_buf_incore() argument
235 return xfs_buf_get_map(target, &map, 1, XBF_INCORE | flags, bpp); in xfs_buf_incore()
243 struct xfs_buf **bpp) in xfs_buf_get() argument
247 return xfs_buf_get_map(target, &map, 1, 0, bpp); in xfs_buf_get()
256 struct xfs_buf **bpp, in xfs_buf_read() argument
261 return xfs_buf_read_map(target, &map, 1, flags, bpp, ops, in xfs_buf_read()
277 struct xfs_buf **bpp);
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/linux/drivers/gpu/drm/
H A Ddrm_fourcc.c35 * @bpp: bits per pixels
38 * Computes a drm fourcc pixel format code for the given @bpp/@depth values.
40 uint32_t drm_mode_legacy_fb_format(uint32_t bpp, uint32_t depth) in drm_mode_legacy_fb_format() argument
44 switch (bpp) { in drm_mode_legacy_fb_format()
88 case 30: in drm_mode_legacy_fb_format()
110 * @bpp: bits per pixels
113 * Computes a drm fourcc pixel format code for the given @bpp/@depth values.
119 uint32_t bpp, uint32_t depth) in drm_driver_legacy_fb_format() argument
121 uint32_t fmt = drm_mode_legacy_fb_format(bpp, depth); in drm_driver_legacy_fb_format()
233 …{ .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .… in __drm_format_info()
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H A Ddrm_gem_framebuffer_helper.c516 return 30; in drm_gem_afbc_get_bpp()
528 /* remove bpp when all users properly encode cpp in drm_format_info */ in drm_gem_afbc_min_size()
529 __u32 bpp; in drm_gem_afbc_min_size() local
564 bpp = drm_gem_afbc_get_bpp(dev, info, mode_cmd); in drm_gem_afbc_min_size()
565 if (!bpp) { in drm_gem_afbc_min_size()
566 drm_dbg_kms(dev, "Invalid AFBC bpp value: %d\n", bpp); in drm_gem_afbc_min_size()
573 afbc_fb->afbc_size += n_blocks * ALIGN(bpp * AFBC_SUPERBLOCK_PIXELS / 8, in drm_gem_afbc_min_size()
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-ldb.yaml19 For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
27 For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
/linux/drivers/video/fbdev/sis/
H A Dsis_accel.h134 bit 30 3D engine: 1 is idle,
180 #define SiS300SetupDSTColorDepth(bpp) \ argument
182 MMIO_OUT16(ivideo->mmio_vbase, BR(1)+2, bpp);\
259 bit 30 = 1: Hardware Queue (=HW CQ, 2D queue, 3D queue) empty
310 #define SiS310SetupDSTColorDepth(bpp) \ argument
312 MMIO_OUT16(ivideo->mmio_vbase, AGP_BASE, bpp);\
/linux/arch/sparc/include/uapi/asm/
H A Dfbio.h141 #define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
176 int mdi_mode; /* 8bpp, 16bpp or 32bpp */
/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h334 # define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30
335 # define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
338 # define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30
339 # define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
358 # define SCALER_DISPCTRLX_RESET BIT(30)
367 /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
396 # define SCALER_DISPBKGND_INTERLACE BIT(30)
407 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
408 # define SCALER_DISPSTATX_MODE_SHIFT 30
473 # define SCALER_GAMADDR_SRAMENB BIT(30)
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/linux/drivers/gpu/drm/radeon/
H A Dcikd.h413 # define LC_GO_TO_RECOVERY (1 << 30)
670 #define TRAIN_DONE_D0 (1 << 30)
990 # define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
993 # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
998 # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
1004 # define FMT_75FRC_SEL(x) ((x) << 30)
1032 #define CPG_BUSY (1 << 30)
1057 #define CB_BUSY (1 << 30)
1072 #define SE_DB_BUSY (1 << 30)
1096 #define MEC_ME1_HALT (1 << 30)
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/linux/arch/arm/mach-pxa/
H A Dam200epd.c49 .bpp = 16,
63 .bpp = 16,
66 .right_margin = 30,
77 .bpp = 16,
249 /* we divide since we told the LCD controller we're 16bpp */ in am200_presetup_fb()
/linux/drivers/video/fbdev/aty/
H A Dmach64_gx.c34 #define MAX_M 30
81 const union aty_pll *pll, u32 bpp, u32 accel) in aty_set_dac_514() argument
92 0, 0x41, 0x03, 0x71, 0x45}, /* 8 bpp */ in aty_set_dac_514()
100 switch (bpp) { in aty_set_dac_514()
119 /* Misc Control 2 / 16 BPP Control / 32 BPP Control */ in aty_set_dac_514()
124 u32 bpp, union aty_pll *pll) in aty_var_to_pll_514() argument
206 const union aty_pll *pll, u32 bpp, in aty_set_dac_ATI68860_B() argument
215 switch (bpp) { in aty_set_dac_ATI68860_B()
289 const union aty_pll *pll, u32 bpp, in aty_set_dac_ATT21C498() argument
299 switch (bpp) { in aty_set_dac_ATT21C498()
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/linux/drivers/gpu/drm/gma500/
H A Dintel_bios.c55 dev_priv->edp.bpp = 18; in parse_edp()
59 dev_priv->edp.bpp); in parse_edp()
67 dev_priv->edp.bpp = 18; in parse_edp()
70 dev_priv->edp.bpp = 24; in parse_edp()
73 dev_priv->edp.bpp = 30; in parse_edp()
102 DRM_DEBUG_KMS("VBT reports EDP: Lane_count %d, Lane_rate %d, Bpp %d\n", in parse_edp()
103 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
/linux/arch/m68k/include/asm/
H A Dfbio.h144 #define FBIO_WID_ALLOC _IOWR('F', 30, struct fb_wid_alloc)
179 int mdi_mode; /* 8bpp, 16bpp or 32bpp */
/linux/drivers/media/platform/xilinx/
H A Dxilinx-vip.h43 #define XVIP_CTRL_CONTROL_FRAME_SYNC_RESET BIT(30)
110 * @bpp: bytes per pixel (when stored in memory)
118 unsigned int bpp; member
/linux/drivers/gpu/drm/arm/
H A Dmalidp_hw.c173 /* All RGB formats > 16bpp (except XRGB, RGBX, XBGR, BGRX) */
396 int bpp = info->cpp[0] * 8; in malidp_format_get_bpp() local
398 if (bpp == 0) { in malidp_format_get_bpp()
401 bpp = 30; in malidp_format_get_bpp()
404 bpp = 15; in malidp_format_get_bpp()
407 bpp = 12; in malidp_format_get_bpp()
410 bpp = 0; in malidp_format_get_bpp()
414 return bpp; in malidp_format_get_bpp()
423 * size = rotated_width * (bpp / 8) * 8; in malidp500_rotmem_required()
425 int bpp = malidp_format_get_bpp(fmt); in malidp500_rotmem_required() local
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h171 /*16 bpp*/
173 /*16 bpp*/
175 /*32 bpp*/
177 /*32 bpp swaped*/
187 /*64 bpp */
324 DC_SW_VAR_D_X = 30,
863 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
991 uint32_t dsc_fixed_bits_per_pixel_x16; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
/linux/include/video/
H A Dsstfb.h173 # define TILES_IN_X_LSB_SHIFT 30 /* v2 */
195 # define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */
234 # define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/
235 # define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/
328 void (*set_vidmod) (struct fb_info *info, const int bpp);

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