Lines Matching +full:30 +full:bpp
334 # define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30
335 # define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
338 # define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30
339 # define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
358 # define SCALER_DISPCTRLX_RESET BIT(30)
367 /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
396 # define SCALER_DISPBKGND_INTERLACE BIT(30)
407 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
408 # define SCALER_DISPSTATX_MODE_SHIFT 30
473 # define SCALER_GAMADDR_SRAMENB BIT(30)
527 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
569 # define SCALER6_DISPX_CTRL0_RESET BIT(30)
868 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
902 # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)
1008 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
1059 /* 8bpp */
1061 /* 16bpp */
1066 /* 24bpp */
1069 /* 32bpp */
1106 #define SCALER_CTL0_VALID BIT(30)
1185 #define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
1186 #define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
1221 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
1222 #define SCALER_POS2_ALPHA_MODE_SHIFT 30
1315 #define SCALER_PPF_AGC BIT(30)
1351 #define SCALER6_CTL0_VALID BIT(30)
1374 #define SCALER6_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
1401 #define SCALER6_PTR2_ALPHA_ORDER_MASK VC4_MASK(30, 30)