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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
45 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
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H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
44 #define MT_RXD1_NORMAL_CM BIT(23)
45 #define MT_RXD1_NORMAL_CLM BIT(24)
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H A Dmt76x02_dma.h1 /* SPDX-License-Identifier: ISC */
13 #define MT_TXD_INFO_NEXT_VLD BIT(16)
14 #define MT_TXD_INFO_TX_BURST BIT(17)
15 #define MT_TXD_INFO_80211 BIT(19)
16 #define MT_TXD_INFO_TSO BIT(20)
17 #define MT_TXD_INFO_CSO BIT(21)
18 #define MT_TXD_INFO_WIV BIT(24)
21 #define MT_TXD_INFO_TYPE GENMASK(31, 30)
24 #define MT_RX_FCE_INFO_SELF_GEN BIT(15)
27 #define MT_RX_FCE_INFO_PCIE_INTR BIT(24)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
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H A Dregs.h1 /* SPDX-License-Identifier: ISC */
35 #define MT_HW_INFO_BASE ((dev)->reg_map[MT_HW_BASE])
40 #define MT_TOP_3NSS BIT(24)
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
59 #define MT_MCU_PCIE_REMAP_2 ((dev)->reg_map[MT_PCIE_REMAP_2])
62 #define MT_PCIE_REMAP_BASE_2 ((dev)->reg_map[MT_PCIE_REMAP_BASE2])
69 #define MT_HIF(ofs) ((dev)->reg_map[MT_HIF_BASE] + (ofs))
71 #define MT_HIF_LOGIC_RST_N BIT(4)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
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/freebsd/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
76 #define RTW89_TXWD_BODY0_STF_MODE BIT(10)
77 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7)
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H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
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H A Drtw8852b_rfk_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
23 RTW89_DECL_RFK_WM(0x20f4, BIT(24), 0x0),
34 RTW89_DECL_RFK_WM(0x20f4, BIT(24), 0x0),
45 RTW89_DECL_RFK_WM(0x032C, BIT(30), 0x0),
48 RTW89_DECL_RFK_WM(0x032C, BIT(16), 0x0),
49 RTW89_DECL_RFK_WM(0x12dc, BIT(0), 0x1),
50 RTW89_DECL_RFK_WM(0x12e8, BIT(2), 0x1),
51 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x8f, BIT(13), 0x1),
57 RTW89_DECL_RFK_WM(0x032C, BIT(30), 0x0),
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
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H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
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/freebsd/contrib/netbsd-tests/include/
H A Dd_bitstring_32.out35 30 3 64 4
39 be: 0 -1 00000000000000000000000000000000
40 is: 0 -1 00000000000000000000000000000000
82 30 0
86 be: 0 -1 00000000000000000000000000000000
87 is: 0 -1 00000000000000000000000000000000
94 be: 0 -1 00000000000000000000000000000000
95 is: 0 -1 00000000000000000000000000000000
98 be: 0 -1 00000000000000000000000000000000
99 is: 0 -1 00000000000000000000000000000000
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H A Dd_bitstring_49.out35 30 3 64 4
56 be: 0 -1 0000000000000000000000000000000000000000000000000
57 is: 0 -1 0000000000000000000000000000000000000000000000000
99 30 0
120 be: 0 -1 0000000000000000000000000000000000000000000000000
121 is: 0 -1 0000000000000000000000000000000000000000000000000
128 be: 0 -1 0000000000000000000000000000000000000000000000000
129 is: 0 -1 0000000000000000000000000000000000000000000000000
132 be: 0 -1 0000000000000000000000000000000000000000000000000
133 is: 0 -1 0000000000000000000000000000000000000000000000000
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H A Dd_bitstring_67.out35 30 3 64 4
74 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
75 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
117 30 0
156 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
157 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
164 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
165 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
168 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
169 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000000
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H A Dd_bitstring_64.out35 30 3 64 4
71 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
72 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
114 30 0
150 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
151 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
158 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
159 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
162 be: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
163 is: 0 -1 0000000000000000000000000000000000000000000000000000000000000000
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/freebsd/contrib/libarchive/libarchive/test/
H A Dtest_zip_filename_encoding.c1 /*-
36 if (NULL == setlocale(LC_ALL, "en_US.UTF-8")) { in DEFINE_TEST()
37 skipping("en_US.UTF-8 locale not available on this system."); in DEFINE_TEST()
42 * Verify that UTF-8 filenames are correctly stored with in DEFINE_TEST()
43 * hdrcharset=UTF-8 option. in DEFINE_TEST()
47 if (archive_write_set_options(a, "hdrcharset=UTF-8") != ARCHIVE_OK) { in DEFINE_TEST()
48 skipping("This system cannot convert character-set" in DEFINE_TEST()
49 " for UTF-8."); in DEFINE_TEST()
57 /* Set a UTF-8 filename. */ in DEFINE_TEST()
65 /* A bit 11 of general purpose flag should be 0x08, in DEFINE_TEST()
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/freebsd/sys/dev/sound/pcm/
H A Dfeeder_rate.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2005-2009 Ariff Abdullah <ariff@FreeBSD.org>
36 * - http://ccrma.stanford.edu/~jos/resample/
39 * + all out fixed point integer operations, no soft-float or anything like
48 * - The z, z_, and Z_ . Due to mental block (or maybe just 0x7a69), I
124 int32_t bps; /* bytes-per-sample */
149 int32_t z_maxfeed; /* maximum feed to avoid 32bit overflow */
164 &feeder_rate_presets, 0, "compile-time rate presets");
176 if (err != 0 || req->newptr == NULL || val == feeder_rate_min) in sysctl_hw_snd_feeder_rate_min()
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/freebsd/sys/dev/ice/
H A Dice_hw_autogen.h1 /* SPDX-License-Identifier: BSD-3-Clause */
37 #define PRTMAC_CTL_TX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE)
38 #define PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_S)
39 #define PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_TX_PAUSE_ENABLE_TX_PAUSE_ENABLE_M : E800_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_M)
40 #define PRTMAC_CTL_RX_PAUSE_ENABLE_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE)
41 #define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S_BY_MAC(hw) ((hw)->mac_type == ICE_MAC_E830 ? E830_PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_S : E800_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_S)
42 #define PRTMAC_CTL_RX_PAUSE_ENABLE_RX_PAUSE_ENABLE_M_BY_MAC(hw) ((hw)->mac_typ
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/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_ia32cap.31 .\" -*- mode: troff; coding: utf-8 -*-
58 .TH OPENSSL_IA32CAP 3ossl 2025-09-30 3.5.4 OpenSSL
64 OPENSSL_ia32cap \- the x86[_64] processor capabilities vector
74 stored internally as ten 32\-bit capability vectors and for simplicity
75 represented logically below as five 64\-bit vectors. This logical
81 environment variable capability bit modifications are applied. After toolkit
94 .IP "bit #0+4 denoting presence of Time-Stamp Counter;" 4
95 .IX Item "bit #0+4 denoting presence of Time-Stamp Counter;"
97 .IP "bit #0+19 denoting availability of CLFLUSH instruction;" 4
98 .IX Item "bit #0+19 denoting availability of CLFLUSH instruction;"
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/freebsd/contrib/bearssl/src/ec/
H A Dec_c25519_m31.c53 j = 30 * (int)u;
57 j -= k;
61 tmp[39 - k - j] |= (unsigned char)w;
74 * that right-shifting a signed negative integer copies the sign bit
75 * (arithmetic right-shift). This is "implementation-defined behaviour",
84 | ((-((uint32_t)(x) >> 31)) << (32 - (n))))
90 * Convert an integer from unsigned little-endian encoding to a sequence of
91 * 30-bit words in little-endian order. The final "partial" word is
102 while (len -- > 0) { in le8_to_le30()
111 acc = b >> (30 - acc_len); in le8_to_le30()
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/freebsd/sys/dev/irdma/
H A Dirdma.h1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
4 * Copyright (c) 2017 - 2022 Intel Corporation
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
48 #define IRDMA_CQPTAIL_CQP_OP_ERR BIT(31)
59 #define IRDMA_GLINT_RATE_INTRL_ENA_M BIT(6)
60 #define IRDMA_GLINT_RATE_INTRL_ENA BIT(6)
63 #define IRDMA_GLINT_DYN_CTL_INTENA BIT(0)
65 #define IRDMA_GLINT_DYN_CTL_CLEARPBA BIT(1)
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/freebsd/crypto/heimdal/doc/
H A Dlayman.asc9 NIST/OSI Implementors' Workshop document SEC-SIG-91-17.
13 Copyright (C) 1991-1993 RSA Laboratories, a division of RSA
16 Public-Key Cryptography Standards (PKCS)" in all material
18 003-903015-110-000-000
39 in another, higher-level part. Abstraction is the hallmark
63 as integers and bit strings to structured types such as sets
66 each ASN.1 type as a string of eight-bit octets. There is
67 generally more than one way to BER-encode a given value.
73 BER and DER sufficient to understand and implement one OSI-
74 based application, RSA Data Security, Inc.'s Public-Key
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600InstrFormats.td1 //===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">;
16 "Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
27 bit Trig = 0;
28 bit Op3 = 0;
29 bit isVector = 0;
31 bit Op1 = 0;
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/freebsd/sys/contrib/libsodium/src/libsodium/crypto_pwhash/scryptsalsa208sha256/
H A Dcrypto_scrypt-common.c1 /*-
36 uint32_t bit; in encode64_uint32() local
38 for (bit = 0; bit < srcbits; bit += 6) { in encode64_uint32()
43 dstlen--; in encode64_uint32()
67 dstlen -= dnext - dst; in encode64()
79 *dst = (uint32_t)(ptr - itoa64); in decode64_one()
84 return -1; in decode64_one()
90 uint32_t bit; in decode64_uint32() local
94 for (bit = 0; bit < dstbits; bit += 6) { in decode64_uint32()
101 value |= one << bit; in decode64_uint32()
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
126 #define __REG(id) (dev->reg.reg_rev[(id)])
127 #define __OFFS(id) (dev->reg.offs_rev[(id)])
140 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
141 #define MT_MCU_INT_EVENT_DMA_INIT BIT(1)
142 #define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
143 #define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
150 #define MT_PLE_HOST_RPT0_TX_LATENCY BIT(3)
175 #define MT_MDP_DCR0_DAMSDU_EN BIT(15)
176 #define MT_MDP_DCR0_RX_HDR_TRANS_EN BIT(19)
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