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/linux/drivers/clocksource/
H A Dscx200_hrt.c5 * This is a clocksource driver for the Geode SCx200's 1 or 27 MHz
25 MODULE_PARM_DESC(mhz27, "count at 27.0 MHz (default is 1.0 MHz)");
36 #define HR_TMCLKSEL (1 << 1) /* 1|0 counts at 27|1 MHz */
39 /* The base timer frequency, * 27 if selected */
79 freq *= 27; in init_hrt_clocksource()
81 pr_info("enabling scx200 high-res timer (%s MHz +%d ppm)\n", mhz27 ? "27":"1", ppm); in init_hrt_clocksource()
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/linux/drivers/video/fbdev/
H A Dvalkyriefb.h79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
155 used to be 20,53,2, pixel clock 41.41MHz for V=59.78Hz */
163 { 14, 27, 2 }, /* pixel clock = 30.13MHz for V=66.43Hz */
[all …]
/linux/drivers/media/pci/cx23885/
H A Dnetup-init.c95 /* set 27MHz on AUX_CLK */
104 /* Aux PLL frac for 27 MHz */ in netup_initialize()
107 /* Aux PLL int for 27 MHz */ in netup_initialize()
/linux/drivers/media/dvb-frontends/
H A Dmxl5xx_defs.h396 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
397 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
398 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
399 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
404 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
433 MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
450 #define MXL_HYDRA_NCO_CLK 418 /* 418 MHz */
[all …]
H A Dmxl5xx_regs.h16 #define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */
17 #define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */
H A Dhorus3a.c186 /* frequency should be X MHz (X : integer) */ in horus3a_set_params()
195 /* Assumed that fREF == 1MHz (1000kHz) */ in horus3a_set_params()
254 * SR * 0.675 + 5 = SR * (27/40) + 5 in horus3a_set_params()
262 fc_lpf = (u8)DIV_ROUND_UP(symbol_rate * 27, 40000) + 5; in horus3a_set_params()
324 .frequency_min_hz = 950 * MHz,
325 .frequency_max_hz = 2150 * MHz,
326 .frequency_step_hz = 1 * MHz,
366 case 27: in horus3a_attach()
/linux/Documentation/devicetree/bindings/rtc/
H A Dbrcm,brcmstb-waketimer.yaml13 The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
38 description: clock reference in the 27MHz domain
/linux/drivers/media/tuners/
H A Dqt1010_priv.h22 07 2b set frequency: 32 MHz scale, n*32 MHz
24 09 10 ? changes every 8/24 MHz; values 1d/1c
25 0a 08 set frequency: 4 MHz scale, n*4 MHz
26 0b 41 ? changes every 2/2 MHz; values 45/45
54 27 29 ?
70 #define QT1010_MIN_FREQ (48 * MHz)
71 #define QT1010_MAX_FREQ (860 * MHz)
72 #define QT1010_OFFSET (1246 * MHz)
/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
/linux/tools/power/x86/x86_energy_perf_policy/
H A Dx86_energy_perf_policy.8124 is in units of 100 MHz, Eg. 12 signifies 1200 MHz.
151 level on this processor, specified in multiples of 100 MHz.
191 cpu0: HWP_CAP: low 1 eff 8 guar 27 high 35
194 cpu1: HWP_CAP: low 1 eff 8 guar 27 high 35
197 cpu2: HWP_CAP: low 1 eff 8 guar 27 high 35
200 cpu3: HWP_CAP: low 1 eff 8 guar 27 high 35
/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h262 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
263 * or 3.5795 MHz).
424 * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
425 * or 3.5795 MHz).
624 * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
625 * 12 MHz, or GPIO [21]).
665 #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
726 #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
727 /* (11.981 MHz) */
728 #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
[all …]
/linux/drivers/clk/
H A Dclk-nspire.c13 #define MHZ (1000 * 1000) macro
44 clk->base_clock = 48 * MHZ; in nspire_clkinfo_cx()
46 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; in nspire_clkinfo_cx()
55 clk->base_clock = 27 * MHZ; in nspire_clkinfo_classic()
57 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; in nspire_clkinfo_classic()
132 info.base_clock / MHZ, in nspire_clk_setup()
133 info.base_clock / info.base_cpu_ratio / MHZ, in nspire_clk_setup()
134 info.base_clock / info.base_ahb_ratio / MHZ); in nspire_clk_setup()
H A Dclk-tps68470.c41 * frequency range of 3 MHz to 27 MHz by a programmable
44 * of 4 MHz to 64 MHz in increments of 0.1 MHz.
53 * BOOST should be as close as possible to 2Mhz
56 * BUCK should be as close as possible to 5.2Mhz
60 * 20Mhz 170 32 1 19.2Mhz
61 * 20Mhz 170 40 1 20Mhz
62 * 20Mhz 170 80 1 24Mhz
/linux/include/media/i2c/
H A Dtc358743.h33 u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */
61 * bps pr lane is 823.5 MHz, and can serve as a starting point.
86 /* Reset PHY automatically when TMDS clock passes 21 MHz.
/linux/drivers/clk/spear/
H A Dspear1310_clock.c26 #define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT 27
73 #define SPEAR1310_I2S_SCLK_X_SHIFT 27
108 #define SPEAR1310_CLCD_CLK_ENB 27
231 /* PCLK 24MHz */
232 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
233 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
234 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
235 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
236 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
237 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt2701.c29 108 * MHZ),
31 400 * MHZ),
35 340 * MHZ),
37 340 * MHZ),
39 340 * MHZ),
41 27 * MHZ),
43 416 * MHZ),
45 143 * MHZ),
47 27 * MHZ),
605 0x012c, 19, 1, 27),
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dsony,imx335.yaml28 description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz
/linux/drivers/watchdog/
H A Dsc520_wdt.c13 * 9/27 - 2001 [Initial release]
37 * 3/27 - 2004 Changes by Sean Young <sean@mess.org>
108 #define WDT_EXP_SEL_01 0x0001 /* [01] Time-out = 496 us (with 33 Mhz clk). */
109 #define WDT_EXP_SEL_02 0x0002 /* [02] Time-out = 508 ms (with 33 Mhz clk). */
110 #define WDT_EXP_SEL_03 0x0004 /* [03] Time-out = 1.02 s (with 33 Mhz clk). */
111 #define WDT_EXP_SEL_04 0x0008 /* [04] Time-out = 2.03 s (with 33 Mhz clk). */
112 #define WDT_EXP_SEL_05 0x0010 /* [05] Time-out = 4.07 s (with 33 Mhz clk). */
113 #define WDT_EXP_SEL_06 0x0020 /* [06] Time-out = 8.13 s (with 33 Mhz clk). */
114 #define WDT_EXP_SEL_07 0x0040 /* [07] Time-out = 16.27s (with 33 Mhz clk). */
115 #define WDT_EXP_SEL_08 0x0080 /* [08] Time-out = 32.54s (with 33 Mhz clk). */
/linux/drivers/gpu/drm/meson/
H A Dmeson_vclk.h22 /* 27MHz is the CVBS Pixel Clock */
23 #define MESON_VCLK_CVBS (27 * 1000 * 1000)
/linux/Documentation/networking/device_drivers/ethernet/chelsio/
H A Dcxgb.rst221 eth#: Chelsio N210 1x10GBaseX NIC (rev #), PCIX 133MHz/64-bit
272 title Red Hat Enterprise Linux AS (2.4.21-27.ELsmp)
274 kernel /vmlinuz-2.4.21-27.ELsmp ro root=/dev/hda3 noirqbalance
275 initrd /initrd-2.4.21-27.ELsmp.img
307 chipset, you may experience the "133-Mhz Mode Split Completion Data
308 Corruption" bug identified by AMD while using a 133Mhz PCI-X card on the
313 is operating at 133 Mhz", causing data corruption.
318 For 133Mhz secondary bus operation, limit the transaction length and
327 section 56, "133-MHz Mode Split Completion Data Corruption" for more
/linux/drivers/phy/ti/
H A Dphy-ti-pipe3.c63 #define INTERFACE_MASK GENMASK(31, 27)
64 #define INTERFACE_SHIFT 27
83 #define MEM_HS_RATE_MASK GENMASK(28, 27)
84 #define MEM_HS_RATE_SHIFT 27
187 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
188 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
189 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
190 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
191 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
192 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
[all …]
/linux/include/linux/platform_data/x86/
H A Dpmc_atom.h56 #define PMC_CLK_FREQ_XTAL (0 << 2) /* 25 MHz */
57 #define PMC_CLK_FREQ_PLL (1 << 2) /* 19.2 MHz */
99 #define PMC_PSS_BIT_CHT_DFX_CLUSTER1 BIT(27)
135 #define BIT_LPSS2_F3_I2C3 BIT(27)
/linux/include/linux/mmc/
H A Dmmc.h66 #define MMC_PROGRAM_CSD 27 /* adtc R1 */
138 #define R1_ERASE_PARAM (1 << 27) /* ex, c */
221 /* (CMD16,24,25,26,27) */
349 #define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
350 #define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
353 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
355 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
359 #define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
360 #define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
364 #define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
[all …]
/linux/drivers/phy/intel/
H A Dphy-intel-keembay-emmc.c21 #define OTAP_DLY_ENA_MASK BIT(27)
59 unsigned int mhz; in keembay_emmc_phy_power() local
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
91 else if (mhz <= 110 && mhz >= 80) in keembay_emmc_phy_power()
93 else if (mhz <= 80 && mhz >= 50) in keembay_emmc_phy_power()
99 if (mhz > 175) in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
[all …]

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