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/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
[all …]
/linux/drivers/clk/ralink/
H A Dclk-mt7621.c71 GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
72 GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
73 GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
74 GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
75 GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
76 GATE(MT7621_CLK_PIO, "pio", "50m", BIT(13)),
78 GATE(MT7621_CLK_NAND, "nand", "125m", BIT(15)),
79 GATE(MT7621_CLK_I2C, "i2c", "50m", BIT(16)),
80 GATE(MT7621_CLK_I2S, "i2s", "270m", BIT(17)),
82 GATE(MT7621_CLK_UART1, "uart1", "50m", BIT(19)),
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt7621-sysc.yaml78 "50m", "125m", "150m",
79 "250m", "270m";
/linux/Documentation/arch/arm/omap/
H A Ddss.rst167 rotate Rotation 0-3 for 0, 90, 180, 270 degrees
201 rotate Rotation 0-3 for 0, 90, 180, 270 degrees
325 "1:4M" to allocate 4M for fb1.
343 3 - 270 degree rotation
/linux/Documentation/hwmon/
H A Dcoretemp.rst11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
71 i7 3920XM, 3820QM, 3720QM, 3667U, 3520M 105
72 i5 3427U, 3360M/3320M 105
83 i7 660UM/640/620, 640LM/620, 620M, 610E 105
84 i5 540UM/520/430, 540M/520/450/430 105
85 i3 330E, 370M/350/330 90 rPGA, 105 BGA
124 N280/270 90
/linux/Documentation/fb/
H A Dmodedb.rst23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
31 - NSTC: 480i output, with the CCIR System-M TV mode and NTSC color encoding
32 - NTSC-J: 480i output, with the CCIR System-M TV mode, the NTSC color
35 - PAL-M: 480i output, with the CCIR System-M TV mode and PAL color encoding
37 If 'M' is specified in the mode_option argument (after <yres> and before
41 If 'i' is specified, calculate for an interlaced mode. And if 'm' is
45 Sample usage: 1024x768M@60m - CVT timing with margins
75 degrees. Valid values are 0, 90, 180 and 270.
77 "PAL-M", "PAL-N", or "SECAM".
125 <pix>M<a>[-R]
[all …]
/linux/drivers/clk/hisilicon/
H A Dcrg-hi3798cv200.c48 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
49 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
50 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
51 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
52 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
53 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
54 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
55 { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
56 { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
58 { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
[all …]
/linux/drivers/staging/fbtft/
H A Dfb_ili9163.c8 * .S.U.M.O.T.O.Y. by Max MC Costa (https://github.com/sumotoy/TFT_ILI9163C).
130 case 270: in set_addr_win()
174 case 270: in set_var()
/linux/drivers/media/dvb-frontends/
H A Ds5h1411.c143 { 0x387, 270, },
186 { 0x14b5, 270, },
315 { 0x53a0, 270, },
475 enum fe_modulation m) in s5h1411_enable_modulation() argument
479 dprintk("%s(0x%08x)\n", __func__, m); in s5h1411_enable_modulation()
481 if ((state->first_tune == 0) && (m == state->current_modulation)) { in s5h1411_enable_modulation()
487 switch (m) { in s5h1411_enable_modulation()
510 state->current_modulation = m; in s5h1411_enable_modulation()
H A Ds5h1409.c116 { 896, 270, },
160 { 22, 270, },
286 { 92, 270, },
391 enum fe_modulation m) in s5h1409_enable_modulation() argument
395 dprintk("%s(0x%08x)\n", __func__, m); in s5h1409_enable_modulation()
397 switch (m) { in s5h1409_enable_modulation()
418 state->current_modulation = m; in s5h1409_enable_modulation()
H A Dau8522_dig.c34 { 0, 270 },
542 enum fe_modulation m) in au8522_enable_modulation() argument
547 dprintk("%s(0x%08x)\n", __func__, m); in au8522_enable_modulation()
549 switch (m) { in au8522_enable_modulation()
590 state->current_modulation = m; in au8522_enable_modulation()
H A Dtda10086.c121 tda10086_write_byte(state, 0x3a, 0x0b); /* M=12 */ in tda10086_init()
124 tda10086_write_byte(state, 0x3a, 0x17); /* M=24 */ in tda10086_init()
306 } else if (symbol_rate < SACLK / 10000 * 270) { in tda10086_set_symbol_rate()
/linux/include/uapi/linux/
H A Dif_arp.h12 * Portions taken from the KA9Q/NOS (v2.00m PA0GRI) source.
53 #define ARPHRD_ROSE 270
/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
24 "Unit": "CPU-M-CF",
31 "Unit": "CPU-M-CF",
38 "Unit": "CPU-M-CF",
45 "Unit": "CPU-M-CF",
52 "Unit": "CPU-M-CF",
59 "Unit": "CPU-M-CF",
66 "Unit": "CPU-M-CF",
[all …]
/linux/drivers/clk/samsung/
H A Dclk-pll.c212 /* Maximum lock time can be 270 * PDIV cycles */
213 #define PLL35XX_LOCK_FACTOR (270)
991 u32 r, p, m, s, pll_stat; in samsung_pll2550x_recalc_rate() local
999 m = (pll_stat >> PLL2550X_M_SHIFT) & PLL2550X_M_MASK; in samsung_pll2550x_recalc_rate()
1002 fvco *= m; in samsung_pll2550x_recalc_rate()
1016 /* Maximum lock time can be 270 * PDIV cycles */
1017 #define PLL2550XX_LOCK_FACTOR 270
1416 /* Set PLL M, P, and S values. */ in samsung_pll1031x_set_rate()
/linux/tools/perf/pmu-events/arch/s390/cf_z17/
H A Dextended.json3 "Unit": "CPU-M-CF",
10 "Unit": "CPU-M-CF",
17 "Unit": "CPU-M-CF",
24 "Unit": "CPU-M-CF",
31 "Unit": "CPU-M-CF",
38 "Unit": "CPU-M-CF",
45 "Unit": "CPU-M-CF",
52 "Unit": "CPU-M-CF",
59 "Unit": "CPU-M-CF",
66 "Unit": "CPU-M-CF",
[all …]
/linux/drivers/gpu/drm/tests/
H A Ddrm_cmdline_parser_test.c298 const char *cmdline = "720x480-24@60m"; in drm_test_cmdline_res_bpp_refresh_margins()
611 const char *cmdline = "720x480,rotate=270"; in drm_test_cmdline_rotate_270()
707 const char *cmdline = "720x480,rotate=270,reflect_x"; in drm_test_cmdline_multiple_options()
857 .cmdline = "m",
909 .cmdline = "NTSC@60m",
1000 TV_OPT_TEST(PAL_M, "720x480i,tv_mode=PAL-M", drm_mode_analog_ntsc_480i),
/linux/tools/net/ynl/pyynl/lib/
H A Dynl.py27 SOL_NETLINK = 270
885 for m in members:
886 if m.type in ['pad', 'binary']:
887 if m.struct:
888 size += self._struct_size(m.struct)
890 size += m.len
892 format = NlAttr.get_format(m.type, m.byte_order)
902 for m in members:
904 if m
[all...]
/linux/arch/m68k/mac/
H A Dconfig.c722 .name = "PowerBook Duo 270c",
782 struct mac_model *m; in mac_identify() local
794 for (m = &mac_data_table[1]; m->ident != -1; m++) { in mac_identify()
795 if (m->ident == model) { in mac_identify()
796 macintosh_config = m; in mac_identify()
/linux/drivers/clk/qcom/
H A Dclk-rcg2.c157 * @f: Frequency table with pure m/n/pre_div parameters.
166 * calc_rate() - Calculate rate based on m/n:d values
169 * @m: Multiplier.
171 * @mode: Use zero to ignore m/n calculation.
177 * parent_rate m
182 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) in calc_rate() argument
188 rate = mult_frac(rate, m, n); in calc_rate()
197 u32 hid_div, m = 0, n = 0, mode = 0, mask; in __clk_rcg2_recalc_rate() local
201 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); in __clk_rcg2_recalc_rate()
202 m &= mask; in __clk_rcg2_recalc_rate()
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-opp-tacoma.dts31 reg = <0xb8000000 0x4000000>; /* 64M */
46 reg = <0xbf000000 0x01000000>; /* 16M */
187 clk-phase-mmc-hs200 = <36>, <270>;
/linux/drivers/pinctrl/
H A Dpinctrl-ep93xx.c561 /* Row M */
667 PINCTRL_PIN(270, "USBm[1]"), /* U16 */
935 /* Row M */
1020 PINCTRL_PIN(270, "ROW[2]"), /* T19 */
1121 234, 235, 248, 249, 251, 270, 271, 291,
1130 234, 235, 248, 249, 251, 270, 271, 291,
/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h76 * 0->3 4 VLC data buffer in DDR (1M each)
692 * 2'b01 phase set to 270 degree
702 * CLK_OUT = CLK_IN * (M+1) / ((N+1) * P)
703 * SYSPLL_M M parameter
758 * 11 270 ~ 700 MHz
984 * H264EN_RATE_CNTL_BUSm_CHn H264 Encoding Path BUS m Rate Control for Channel n
1056 * 0 256M DDR on board
1057 * 1 512M DDR on board
1652 * 0 NTSC (M)
1656 * 4 PAL (M)
[all …]
/linux/sound/soc/codecs/
H A Dmt6357.c58 * will also have 26m, so will have power leak in set_capture_gpio()
828 usleep_range(250, 270); in configure_downlinks()
994 usleep_range(250, 270); in mt_delay_250_event()
997 usleep_range(250, 270); in mt_delay_250_event()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_audio.c381 * Let's disable "Enable CTS or M Prog bit" in hsw_hdmi_audio_config_update()
907 u8 m; member
919 aud_ts->m = 60; in get_aud_ts_cdclk_m_n()
920 aud_ts->n = cdclk * aud_ts->m / 24000; in get_aud_ts_cdclk_m_n()
932 intel_de_write(display, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN); in intel_audio_cdclk_change_post()
933 drm_dbg_kms(display->drm, "aud_ts_cdclk set to M=%u, N=%u\n", in intel_audio_cdclk_change_post()
934 aud_ts.m, aud_ts.n); in intel_audio_cdclk_change_post()
1032 * 270 | 320 or higher in intel_audio_min_cdclk()

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