Lines Matching +full:270 +full:m
157 * @f: Frequency table with pure m/n/pre_div parameters.
166 * calc_rate() - Calculate rate based on m/n:d values
169 * @m: Multiplier.
171 * @mode: Use zero to ignore m/n calculation.
177 * parent_rate m
182 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
188 rate = mult_frac(rate, m, n);
197 u32 hid_div, m = 0, n = 0, mode = 0, mask;
201 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
202 m &= mask;
206 n += m;
215 return calc_rate(parent_rate, m, n, mode, hid_div);
273 do_div(tmp, f->m);
315 rate = calc_rate(parent_rate, conf->n, conf->m, conf->n, conf->pre_div);
381 do_div(tmp, conf->m);
440 u16 m, n = 1, n_candidate = 1, n_max;
443 m = div64_u64(rate, rates_gcd);
445 while (scaled_parent_rate > (mnd_max + m) * pre_div_max) {
447 if (m > 1) {
448 m--;
449 scaled_parent_rate = mult_frac(scaled_parent_rate, m, (m + 1));
452 f->n = mnd_max + m;
454 f->m = m;
459 n_max = m + mnd_max;
476 f->m = m;
498 req->rate = calc_rate(parent_rate, f->m, f->n, f->n, f->pre_div);
526 RCG_M_OFFSET(rcg), mask, f->m);
531 RCG_N_OFFSET(rcg), mask, ~(f->n - f->m));
538 n_minus_m = f->n - f->m;
541 d_val = clamp_t(u32, d_val, f->m, n_minus_m);
553 if (rcg->mnd_width && f->n && (f->m != f->n))
661 f_tbl.m = conf->m;
722 u32 notn_m, n, m, d, not2d, mask;
732 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
735 if (!not2d && !m && !notn_m) {
747 n = (~(notn_m) + m) & mask;
758 u32 notn_m, n, m, d, not2d, mask, duty_per, cfg;
768 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
775 n = (~(notn_m) + m) & mask;
788 if ((d / 2) > (n - m))
789 d = (n - m) * 2;
790 else if ((d / 2) < (m / 2))
791 d = m;
866 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
867 { 52, 295 }, /* 119 M */
868 { 11, 57 }, /* 130.25 M */
869 { 63, 307 }, /* 138.50 M */
870 { 11, 50 }, /* 148.50 M */
871 { 47, 206 }, /* 154 M */
872 { 31, 100 }, /* 205.25 M */
873 { 107, 269 }, /* 268.50 M */
877 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
878 { 31, 211 }, /* 119 M */
879 { 32, 199 }, /* 130.25 M */
880 { 63, 307 }, /* 138.50 M */
881 { 11, 60 }, /* 148.50 M */
882 { 50, 263 }, /* 154 M */
883 { 31, 120 }, /* 205.25 M */
884 { 119, 359 }, /* 268.50 M */
918 f.m = frac->num;
1182 f.m = frac->num;
1388 * In case clock is disabled, update the M, N and D registers, cache
1635 f->m = val;
1641 val += f->m;
1645 f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div);
1687 u32 level, mask, cfg, m = 0, n = 0, mode, pre_div;
1717 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);
1718 m &= mask;
1724 n += m;
1727 return calc_rate(parent_rate, m, n, mode, pre_div);
1813 f.m = num;
1816 f.m = 0;