Lines Matching +full:270 +full:m
12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
13 UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
36 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
37 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
106 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
134 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */