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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
H A Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
H A Dnxp,tja11xx.yaml54 typically derived from an external 25MHz crystal. Alternatively,
55 a 50MHz clock signal generated by an external oscillator can be
56 connected to pin REF_CLK. A third option is to connect a 25MHz
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dintegratorcp.dts49 /* The codec chrystal operates at 24.576 MHz */
65 /* This is a 25MHz chrystal on the base board */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
87 /* 24 MHz chrystal on the core module */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
149 /* TIMER0 runs directly on the 25MHz chrystal */
155 /* TIMER1 runs @ 1MHz */
161 /* TIMER2 runs @ 1MHz */
286 interrupts = <25>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dsophgo,sg2042-pll.yaml21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
H A Didt,versaclock5.txt66 /* 25MHz reference crystal */
81 /* Connect XIN input to 25MHz reference */
H A Dsilabs,si5351.txt61 /* 25MHz reference crystal */
78 /* connect xtal input to 25MHz reference */
91 * - set initial clock frequency of 74.25MHz
H A Dallwinner,sun7i-a20-gmac-clk.yaml26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
H A Didt,versaclock5.yaml157 /* 25MHz reference crystal */
175 /* Connect XIN input to 25MHz reference */
/freebsd/sys/arm/freescale/imx/
H A Dimx6_anatop.c119 * 396MHz, it also says that the ARM and SOC voltages can't differ by
124 uint32_t mhz; member
136 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
184 newtarg = (mv - 700) / 25; in vdd_set()
190 * (1150-700/25=18). in vdd_set()
197 * 25mV step upward; we actually delay 6uS because empirically, it works in vdd_set()
209 delay = (700 / 25) * 6; in vdd_set()
226 sc->cpu_curmv = newtarg * 25 + 700; in vdd_set()
266 d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz); in cpufreq_nearest_oppt()
281 if (op->mhz > sc->cpu_curmhz) { in cpufreq_set_clock()
[all …]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_common.c1375 * @freq: Frequency (MHz) to convert
1594 /* EDMG channels 25 - 27 */ in ieee80211_freq_to_channel_ext()
1701 case 32: /* channels 1..7; 40 MHz */ in ieee80211_chan_to_freq_us()
1702 case 33: /* channels 5..11; 40 MHz */ in ieee80211_chan_to_freq_us()
1708 case 22: /* channels 36,44; 40 MHz */ in ieee80211_chan_to_freq_us()
1709 case 23: /* channels 52,60; 40 MHz */ in ieee80211_chan_to_freq_us()
1710 case 27: /* channels 40,48; 40 MHz */ in ieee80211_chan_to_freq_us()
1711 case 28: /* channels 56,64; 40 MHz */ in ieee80211_chan_to_freq_us()
1716 case 24: /* channels 100-140; 40 MHz */ in ieee80211_chan_to_freq_us()
1721 case 25: /* channels 149,157; 40 MHz */ in ieee80211_chan_to_freq_us()
[all …]
H A Dhw_features_common.c138 "HT40: control channel: %d (%d MHz), secondary channel: %d (%d MHz)", in allowed_ht40_channel_pair()
141 /* Verify that HT40 secondary channel is an allowed 20 MHz in allowed_ht40_channel_pair()
291 wpa_printf(MSG_DEBUG, "Found overlapping 20 MHz HT BSS: " in check_20mhz_bss()
314 affected_start = (pri_freq + sec_freq) / 2 - 25; in check_40mhz_2g4()
315 affected_end = (pri_freq + sec_freq) / 2 + 25; in check_40mhz_2g4()
316 wpa_printf(MSG_DEBUG, "40 MHz affected channel range: [%d,%d] MHz", in check_40mhz_2g4()
324 /* Check for overlapping 20 MHz BSS */ in check_40mhz_2g4()
328 "Overlapping 20 MHz BSS is found"); in check_40mhz_2g4()
352 "40 MHz pri/sec mismatch with BSS " in check_40mhz_2g4()
373 "40 MHz Intolerant is set on channel %d in BSS " in check_40mhz_2g4()
[all …]
/freebsd/sys/dev/sfxge/common/
H A Def10_tlv_layout.h459 uint16_t clk_sys; /* MHz */
460 uint16_t clk_dpcpu; /* MHz */
461 uint16_t clk_icore; /* MHz */
462 uint16_t clk_pcs; /* MHz */
470 uint16_t clk_sys; /* MHz */
471 uint16_t clk_mc; /* MHz */
472 uint16_t clk_rmon; /* MHz */
473 uint16_t clk_vswitch; /* MHz */
474 uint16_t clk_dpcpu; /* MHz */
475 uint16_t clk_pcs; /* MHz */
[all …]
/freebsd/contrib/wpa/src/ap/
H A Dieee802_11_ht.c73 host_to_le16(25); in hostapd_eid_ht_capabilities()
115 - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or
116 - all STAs in the BSS are 20 MHz HT in 20 MHz BSS
120 however and at least one 20 MHz HT STA is associated
195 affected_start = (pri_freq + sec_freq) / 2 - 25; in is_40_allowed()
196 affected_end = (pri_freq + sec_freq) / 2 + 25; in is_40_allowed()
200 wpa_printf(MSG_ERROR, "40 MHz affected channel range: [%d,%d] MHz", in is_40_allowed()
229 "Ignore 20/40 BSS Coexistence Management frame since 40 MHz capability is not enabled"); in hostapd_2040_coex_action()
267 /* Intra-BSS communication prohibiting 20/40 MHz BSS operation in hostapd_2040_coex_action()
279 "20 MHz BSS width request bit is set in BSS coexistence information field"); in hostapd_2040_coex_action()
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h14 * bandwidths <= 80MHz
16 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
37 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
38 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
39 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
40 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
41 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
122 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
123 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
146 * <nss, channel-width> pair (0 - 80mhz widt
[all...]
/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dksz.txt24 125MHz instead of 25MHz.
42 cs-gpios = <&pioC 25 0>;
/freebsd/sys/contrib/dev/athk/ath10k/
H A Drx_desc.h38 RX_ATTENTION_FLAGS_DIRECTED = BIT(25),
766 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
770 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
774 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
778 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
782 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
786 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
790 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
794 * RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth.
798 * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Ddove-cubox.dts45 /* 25MHz reference crystal */
97 /* connect xtal input to 25MHz reference */
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c101 #define PLLA_IDDQ_BIT 25
270 /* PLLM: 880 MHz Clock source for EMC 2x clock */
282 /* PLLMB: 880 MHz Clock source for EMC 2x clock */
306 /* PLLC: 510 MHz Clock source for camera use */
317 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */
328 /* PLLC3: 510 MHz Clock source for NVENC, NVDEC scaling */
339 /* PLLC4: 600 MHz Clock source for SD/eMMC ans system busses */
352 /* PLLP: 408 MHz Clock source for most peripherals */
391 /* PLLU: 480 MHz Clock source for USB PHY, provides 12/60/480 MHz */
404 /* PLLD: 594 MHz Clock sources for the DSI and display subsystem */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9002/
H A Dar9280.c54 * Take the MHz channel value and set the Channel value
62 * (freq_ref = 40MHz)
66 * (freq_ref = 40MHz/(24>>amodeRefSel))
68 * For 5GHz channels which are 5MHz spaced,
70 * (freq_ref = 40MHz)
134 /* Enable 2G (fractional) mode for channels which are 5MHz spaced */ in ar9280SetChannel()
137 * Workaround for talking on PSB non-5MHz channels; in ar9280SetChannel()
138 * the pre-Merlin chips only had a 2.5MHz channel in ar9280SetChannel()
146 * resolution in this reference is 2.5MHz) and thus in ar9280SetChannel()
182 ch = (((f - 4800) * 10) / 25) + 1; in ar9280SetChannel()
[all …]
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipcreg.h278 #define CHIPC_PLL_TYPE1 0x2 /* 48MHz base, 3 dividers */
279 #define CHIPC_PLL_TYPE2 0x4 /* 48MHz, 4 dividers */
280 #define CHIPC_PLL_TYPE3 0x6 /* 25MHz, 2 dividers */
281 #define CHIPC_PLL_TYPE4 0x1 /* 48MHz, 4 dividers */
282 #define CHIPC_PLL_TYPE5 0x3 /* 25MHz, 4 dividers */
284 #define CHIPC_PLL_TYPE7 0x7 /* 25MHz, 4 dividers */
289 #define CHIPC_XTALMINFREQ 19800000 /* 20 MHz - 1% */
290 #define CHIPC_XTALMAXFREQ 20200000 /* 20 MHz + 1% */
291 #define CHIPC_PCIMINFREQ 25000000 /* 25 MHz */
292 #define CHIPC_PCIMAXFREQ 34000000 /* 33 MHz + fudge */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6sl-warp.dts66 <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
169 pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
185 pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
212 pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
223 pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211phy.h45 #define AR_PHY_PLL_CTL_44 0x19 /* 44 MHz for 11b channels and FPGA */
46 #define AR_PHY_PLL_CTL_40 0x18 /* 40 MHz */
47 #define AR_PHY_PLL_CTL_20 0x13 /* 20 MHz half rate 11a for emulation */
67 #define AR_PHY_PAPD_PROBE_GAINF_S 25
/freebsd/sys/contrib/ncsw/Peripherals/FM/MAC/
H A Dtgec_mii_acc.c62 /* (one half of fm clock => 2.5Mhz) */ in TGEC_MII_WritePhyReg()
63 cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT); in TGEC_MII_WritePhyReg()
106 /* (one half of fm clock => 2.5Mhz) */ in TGEC_MII_ReadPhyReg()
107 cfgStatusReg |=((((p_Tgec->fmMacControllerDriver.clkFreq*10)/2)/25) << MIIMCOM_DIV_SHIFT); in TGEC_MII_ReadPhyReg()

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