/linux/arch/arm64/boot/dts/marvell/ |
H A D | armada-3720-eDPU.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 5 #include "armada-3720-uDPU.dtsi" 13 phy-mode = "2500base-x"; 18 * U-Boot will enable the MDIO bus and switch nodes. 22 pinctrl-names = "default"; 23 pinctrl-0 = <&smi_pins>; 32 #address-cells = <1>; 33 #size-cells = <0>; 38 phy-mode = "2500base-x"; [all …]
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H A D | armada-3720-turris-mox.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 /dts-v1/; 9 #include <dt-bindings/bus/moxtet.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/input/input.h> 12 #include "armada-372x.dtsi" 16 compatible = "cznic,turris-mox", "marvell,armada3720", 28 stdout-path = "serial0:115200n8"; 37 compatible = "gpio-leds"; 41 linux,default-trigger = "default-on"; [all …]
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/linux/arch/arm64/boot/dts/freescale/ |
H A D | fsl-ls1028a-qds-7777.dtso | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * Copyright 2019-2021 NXP 8 * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing 12 /dts-v1/; 16 #address-cells = <1>; 17 #size-cells = <0>; 20 slot1_sxgmii0: ethernet-phy@0 { 22 compatible = "ethernet-phy-ieee802.3-c45"; 25 slot1_sxgmii1: ethernet-phy@1 { 27 compatible = "ethernet-phy-ieee802.3-c45"; [all …]
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/linux/drivers/net/phy/ |
H A D | sfp-bus.c | 1 // SPDX-License-Identifier: GPL-2.0-only 14 * struct sfp_bus - internal representation of a sfp bus 36 * sfp_parse_port() - Parse the EEPROM base ID, setting the port type 43 * %PORT_TP, %PORT_FIBRE or %PORT_OTHER. If @support is non-%NULL, 55 switch (id->base.connector) { in sfp_parse_port() 76 if (id->base.e1000_base_t) { in sfp_parse_port() 88 dev_warn(bus->sfp_dev, "SFP: unknown connector id 0x%02x\n", in sfp_parse_port() 89 id->base.connector); in sfp_parse_port() 111 * sfp_may_have_phy() - indicate whether the module may have a PHY 120 if (id->base.e1000_base_t) in sfp_may_have_phy() [all …]
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/linux/Documentation/networking/dsa/ |
H A D | sja1105.rst | 8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches: 10 - SJA1105E: First generation, no TTEthernet 11 - SJA1105T: First generation, TTEthernet 12 - SJA1105P: Second generation, no TTEthernet, no SGMII 13 - SJA1105Q: Second generation, TTEthernet, no SGMII 14 - SJA1105R: Second generation, no TTEthernet, SGMII 15 - SJA1105S: Second generation, TTEthernet, SGMII 16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and 17 100base-TX PHYs 18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX [all …]
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/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt7986b-rfb.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 12 chassis-type = "embedded"; 13 compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; 20 stdout-path = "serial0:115200n8"; 37 compatible = "mediatek,eth-mac"; 39 phy-mode = "2500base-x"; 41 fixed-link { 42 speed = <2500>; 43 full-duplex; [all …]
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H A D | mt7986a-bananapi-bpi-r3.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 5 * Frank Wunderlich <frank-w@public-files.de> 9 /dts-v1/; 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/input/input.h> 12 #include <dt-bindings/leds/common.h> 13 #include <dt-bindings/pinctrl/mt65xx.h> 18 model = "Bananapi BPI-R3"; 19 chassis-type = "embedded"; 20 compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; [all …]
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H A D | mt7986a-bananapi-bpi-r3-mini.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 4 * Authors: Frank Wunderlich <frank-w@public-files.de> 9 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/leds/common.h> 14 #include <dt-bindings/pinctrl/mt65xx.h> 19 model = "Bananapi BPI-R3 Mini"; 20 chassis-type = "embedded"; 21 compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a"; [all …]
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H A D | mt7986a-rfb.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 /dts-v1/; 8 #include <dt-bindings/pinctrl/mt65xx.h> 14 chassis-type = "embedded"; 15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; 22 stdout-path = "serial0:115200n8"; 30 reg_1p8v: regulator-1p8v { 31 compatible = "regulator-fixed"; 32 regulator-name = "fixed-1.8V"; 33 regulator-min-microvolt = <1800000>; [all …]
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H A D | mt7622-rfb1.dts | 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 9 /dts-v1/; 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/gpio/gpio.h> 18 chassis-type = "embedded"; 19 compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; 26 stdout-path = "serial0:115200n8"; 32 proc-supply = <&mt6380_vcpu_reg>; 33 sram-supply = <&mt6380_vm_reg>; 37 proc-supply = <&mt6380_vcpu_reg>; [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | transmit-amplitude.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 Binding describing the peak-to-peak transmit amplitude for common PHYs 14 - Marek Behún <kabel@kernel.org> 17 tx-p2p-microvolt: 19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property 21 'tx-p2p-microvolt-names' property must be provided and contain 24 tx-p2p-microvolt-names: [all …]
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/linux/arch/arm64/boot/dts/qcom/ |
H A D | sa8775p-ride-r3.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 6 /dts-v1/; 8 #include "sa8775p-ride.dtsi" 12 compatible = "qcom,sa8775p-ride-r3", "qcom,sa8775p"; 16 phy-mode = "2500base-x"; 20 phy-mode = "2500base-x"; 24 compatible = "snps,dwmac-mdio"; 25 #address-cells = <1>; 26 #size-cells = <0>; 29 compatible = "ethernet-phy-id31c3.1c33"; [all …]
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/linux/drivers/regulator/ |
H A D | twl-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * twl-regulator.c -- support regulators in twl4030/twl6030 family chips 25 * These chips are often used in OMAP-based systems. 27 * This driver implements software-based resource control for various 34 u8 base; member 39 /* voltage in mV = table[VSEL]; table_len must be a power-of-two */ 57 /* LDO control registers ... offset is from the base of its register bank. 81 &value, info->base + offset); in twlreg_read() 90 value, info->base + offset); in twlreg_write() 93 /*----------------------------------------------------------------------*/ [all …]
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/linux/Documentation/devicetree/bindings/net/dsa/ |
H A D | mscc,ocelot.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Vladimir Oltean <vladimir.oltean@nxp.com> 11 - Claudiu Manoil <claudiu.manoil@nxp.com> 12 - Alexandre Belloni <alexandre.belloni@bootlin.com> 13 - UNGLinuxDriver@microchip.com 16 There are multiple switches which are either part of the Ocelot-1 family, or 22 Frame DMA or register-based I/O. 26 This is found in the NXP T1040, where it is a memory-mapped platform [all …]
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H A D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Arınç ÜNAL <arinc.unal@arinc9.com> 11 - Landen Chao <Landen.Chao@mediatek.com> 12 - DENG Qingfang <dqfext@gmail.com> 13 - Sean Wang <sean.wang@mediatek.com> 14 - Daniel Golle <daniel@makrotopia.org> 17 There are three versions of MT7530, standalone, in a multi-chip module and 18 built-into a SoC. [all …]
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/linux/Documentation/devicetree/bindings/net/ |
H A D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - $ref: ethernet-phy.yaml# 14 - Andrew Davis <afd@ti.com> 17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver 18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and 19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and 20 100BASE-FX Fiber protocols. 23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX [all …]
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H A D | mediatek,net.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Bianconi <lorenzo@kernel.org> 11 - Felix Fietkau <nbd@nbd.name> 20 - mediatek,mt2701-eth 21 - mediatek,mt7623-eth 22 - mediatek,mt7621-eth 23 - mediatek,mt7622-eth 24 - mediatek,mt7629-eth [all …]
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H A D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - David S. Miller <davem@davemloft.net> 19 local-mac-address: 22 $ref: /schemas/types.yaml#/definitions/uint8-array 26 mac-address: 31 local-mac-address property. 32 $ref: /schemas/types.yaml#/definitions/uint8-array [all …]
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H A D | marvell,pp2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marcin Wojtas <mw@semihalf.com> 11 - Russell King <linux@armlinux.org> 21 - marvell,armada-375-pp2 22 - marvell,armada-7k-pp22 28 "#address-cells": 31 "#size-cells": 37 - description: main controller clock [all …]
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H A D | microchip,lan966x-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Horatiu Vultur <horatiu.vultur@microchip.com> 13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with 14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs, 15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to 16 2 Quad-SGMII/Quad-USGMII interfaces. 20 pattern: "^switch@[0-9a-f]+$" [all …]
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/linux/arch/arm/boot/dts/nxp/vf/ |
H A D | vf610-zii-scu4-aib.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 // Copyright (C) 2016-2018 Zodiac Inflight Innovations 5 /dts-v1/; 10 compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610"; 13 stdout-path = &uart0; 21 gpio-leds { 22 compatible = "gpio-leds"; 23 pinctrl-0 = <&pinctrl_leds_debug>; 24 pinctrl-names = "default"; 26 led-debug { [all …]
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/linux/arch/arm/boot/dts/marvell/ |
H A D | armada-385-clearfog-gtr-s4.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 #include "armada-385-clearfog-gtr.dtsi" 7 compatible = "solidrun,clearfog-gtr-s4", "marvell,armada385", 12 tx-fault-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>; 16 switch0: ethernet-switch@4 { 19 pinctrl-names = "default"; 20 pinctrl-0 = <&cf_gtr_switch_reset_pins>; 21 reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; 23 ethernet-ports { 24 #address-cells = <1>; [all …]
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H A D | armada-385-clearfog-gtr-l8.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 #include "armada-385-clearfog-gtr.dtsi" 7 compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385", 11 sfp1: sfp-1 { 13 pinctrl-0 = <&cf_gtr_sfp1_pins>; 14 pinctrl-names = "default"; 15 i2c-bus = <&i2c0>; 16 mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>; 17 tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; 22 switch0: ethernet-switch@4 { [all …]
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/linux/drivers/iio/adc/ |
H A D | aspeed_adc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Aspeed AST2400/2500/2600 ADC 16 #include <linux/clk-provider.h> 111 void __iomem *base; member 184 dev_warn(data->dev, "Couldn't find syscon node\n"); in aspeed_adc_set_trim_data() 185 return -EOPNOTSUPP; in aspeed_adc_set_trim_data() 190 dev_warn(data->dev, "Failed to get syscon regmap\n"); in aspeed_adc_set_trim_data() 191 return -EOPNOTSUPP; in aspeed_adc_set_trim_data() 193 if (data->model_data->trim_locate) { in aspeed_adc_set_trim_data() 194 if (regmap_read(scu, data->model_data->trim_locate->offset, in aspeed_adc_set_trim_data() [all …]
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/linux/Documentation/ABI/testing/ |
H A D | sysfs-class-net-phydev | 24 This attribute contains the 32-bit PHY Identifier as reported 41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii, 42 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii 43 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui, 44 xaui, 10gbase-kr, unknown 60 32-bit hexadecimal number representing a bit mask of the
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