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/linux/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 on run-time.
20 are used to configure SMMU and GIC-ITS respectively.
22 iommu-map property is used to define the set of stream ids
26 The msi-map property is used to associate the devices with the
34 - Nipun Gupta <nipun.gupta@amd.com>
35 - Nikhil Agarwal <nikhil.agarwal@amd.com>
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt2701.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-mtk-common.h"
15 #include "pinctrl-mtk-mt2701.h"
19 * - For special pins' mode setting
200 MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2),
209 MTK_PIN_DRV_GRP(259, 0xc90, 0, 2),
259 MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14), /* ms0e dat7 */
268 MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10), /* ms0e clk */
334 MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4),
[all …]
/linux/tools/perf/arch/sparc/entry/syscalls/
H A Dsyscall.tbl1 # SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
301 250 32 mremap sys_mremap
302 250 64 mremap sys_64_mremap
315 259 32 clock_nanosleep sys_clock_nanosleep_time32
316 259 64 clock_nanosleep sys_clock_nanosleep
/linux/arch/sparc/kernel/syscalls/
H A Dsyscall.tbl1 # SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
301 250 32 mremap sys_mremap
302 250 64 mremap sys_64_mremap
315 259 32 clock_nanosleep sys_clock_nanosleep_time32
316 259 64 clock_nanosleep sys_clock_nanosleep
/linux/drivers/pinctrl/intel/
H A Dpinctrl-tigerlake.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2019 - 2020, Intel Corporation
17 #include "pinctrl-intel.h"
35 .size = ((e) - (s) + 1), \
45 /* Tiger Lake-LP */
309 PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"),
319 PINCTRL_PIN(259, "DBG_PMODE"),
359 TGL_GPP(3, 226, 250, 320), /* GPP_E */
360 TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */
371 TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
[all …]
/linux/include/dt-bindings/pinctrl/
H A Dmt6797-pinfunc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <dt-bindings/pinctrl/mt65xx.h>
1279 #define MT6797_GPIO250__FUNC_GPIO250 (MTK_PIN_NO(250) | 0)
1280 #define MT6797_GPIO250__FUNC_SPI3_MI (MTK_PIN_NO(250) | 1)
1281 #define MT6797_GPIO250__FUNC_SPI3_MO (MTK_PIN_NO(250) | 2)
1282 #define MT6797_GPIO250__FUNC_IRTX_OUT (MTK_PIN_NO(250) | 3)
1283 #define MT6797_GPIO250__FUNC_TP_URXD1_AO (MTK_PIN_NO(250) | 6)
1284 #define MT6797_GPIO250__FUNC_DROP_ZONE (MTK_PIN_NO(250) | 7)
1345 #define MT6797_GPIO259__FUNC_GPIO259 (MTK_PIN_NO(259) | 0)
1346 #define MT6797_GPIO259__FUNC_IO_JTAG_TDI (MTK_PIN_NO(259) | 1)
[all …]
/linux/include/dt-bindings/clock/
H A Drk3399-cru.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Author: Xing Zheng <zhengxing@rock-chips.com>
198 #define ACLK_GIC 250
207 #define ACLK_ADB400M_PD_CORE_B 259
338 /* pmu-clocks indices */
379 /* soft-reset indices */
630 #define SRST_C_DP_CTRL 250
639 #define SRST_DPTX_SPDIF_REC 259
712 /* pmu soft-reset indices */
H A Dcix,sky1.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
3 * Copyright 2024-2025 Cix Technology Group Co., Ltd.
259 #define CLK_TREE_FCH_SPI0_APB 250
268 #define CLK_TREE_FCH_I2C6_APB 259
H A Dimx6qdl-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
260 #define IMX6QDL_CLK_PRE0 250
269 #define IMX6QDL_CLK_MLB_SEL 259
H A Dqcom,gcc-ipq806x.h1 /* SPDX-License-Identifier: GPL-2.0-only */
252 #define PCIE_1_AUX_CLK 250
261 #define PCIE_2_ALT_REF_SRC 259
H A Dg12a-clkc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */
3 * Meson-G12A clock tree IDs
261 #define CLKID_DSU_CLK_DYN 250
270 #define CLKID_SPICC1_SCLK_SEL 259
H A Dimx6sx-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
259 #define IMX6SX_CLK_PLL1 250
268 #define IMX6SX_PLL3_BYPASS 259
H A Dqcom,gcc-mdm9615.h1 /* SPDX-License-Identifier: GPL-2.0-only */
260 #define GP2_SRC 250
269 #define EBI1_CH0_CA_CLK 259
H A Dqcom,gcc-msm8960.h1 /* SPDX-License-Identifier: GPL-2.0-only */
258 #define GP2_SRC 250
267 #define EBI1_CH0_CA_CLK 259
H A Dqcom,gcc-msm8974.h1 /* SPDX-License-Identifier: GPL-2.0-only */
259 #define GCC_SYS_NOC_QDSS_STM_AXI_CLK 250
268 #define GCC_USB2B_PHY_SLEEP_CLK 259
H A Drk3568-cru.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
10 /* pmucru-clocks indices */
67 /* cru-clocks indices */
314 #define DCLK_EBC 250
323 #define ACLK_RKVENC 259
488 /* pmu soft-reset indices */
504 /* soft-reset indices */
716 #define SRST_I_VICAP 250
726 #define SRST_A_VOP_NIU 259
H A Dqcom,gcc-apq8084.h1 /* SPDX-License-Identifier: GPL-2.0-only */
259 #define GCC_SDCC1_CDCCAL_SLEEP_CLK 250
268 #define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259
H A Dpx30-cru.h1 /* SPDX-License-Identifier: GPL-2.0 */
126 #define HCLK_ISP 250
135 #define HCLK_HOST 259
178 /* pmu-clocks indices */
196 /* soft-reset indices */
H A Dtegra124-car-common.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This header provides constants for binding nvidia,tegra124-car or
4 * nvidia,tegra132-car.
279 /* 250 */
289 #define TEGRA124_CLK_SCLK 259
/linux/include/uapi/sound/
H A Dsnd_ar_tokens.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
34 /* container graph position Stream-Device */
230 #define AR_TKN_U32_MODULE_HW_IF_IDX 250
239 #define AR_TKN_U32_MODULE_LOG_CODE 259
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9261ek.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board
5 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
7 /dts-v1/;
16 stdout-path = "serial0:115200n8";
25 clock-frequency = <32768>;
29 clock-frequency = <18432000>;
40 atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>;
44 bits-per-pixel = <16>;
45 atmel,lcdcon-backlight;
[all …]
/linux/include/dt-bindings/reset/
H A Dqcom,ipq5424-gcc.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
259 #define GCC_Q6_AXIM_RESET 250
268 #define GCC_WCSS_AHB_S_RESET 259
/linux/include/dt-bindings/arm/
H A Dqcom,ids.h1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
12 * older chipsets (qcom,msm-id) and in socinfo driver:
112 #define QCOM_ID_MSM8616 250
117 #define QCOM_ID_MSM8208 259
298 * DTS for older chipsets (qcom,board-id):
/linux/arch/sh/kernel/cpu/sh2a/
H A Dsetup-sh7264.c1 // SPDX-License-Identifier: GPL-2.0
129 INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
133 INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
241 .name = "sh-sci",
265 .name = "sh-sci",
289 .name = "sh-sci",
313 .name = "sh-sci",
331 DEFINE_RES_IRQ(250),
337 .name = "sh-sci",
361 .name = "sh-sci",
[all …]
/linux/drivers/gpu/drm/vmwgfx/device_include/
H A Dsvga3d_devcaps.h1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
3 * Copyright 1998-2021 VMware, Inc.
28 * svga3d_devcaps.h --
57 #define SVGA3D_DEVCAP_INVALID ((uint32)-1)
336 #define SVGA3D_DEVCAP_DEAD12 250
348 #define SVGA3D_DEVCAP_MULTISAMPLE_8X 259

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