1*03e525c6SSricharan Ramabadhran /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*03e525c6SSricharan Ramabadhran /* 3*03e525c6SSricharan Ramabadhran * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. 4*03e525c6SSricharan Ramabadhran * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5*03e525c6SSricharan Ramabadhran */ 6*03e525c6SSricharan Ramabadhran 7*03e525c6SSricharan Ramabadhran #ifndef _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H 8*03e525c6SSricharan Ramabadhran #define _DT_BINDINGS_RESET_IPQ_GCC_IPQ5424_H 9*03e525c6SSricharan Ramabadhran 10*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_BCR 0 11*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_I2C0_BCR 1 12*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_UART0_BCR 2 13*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_I2C1_BCR 3 14*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_UART1_BCR 4 15*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_SPI0_BCR 5 16*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_SPI1_BCR 6 17*03e525c6SSricharan Ramabadhran #define GCC_IMEM_BCR 7 18*03e525c6SSricharan Ramabadhran #define GCC_TME_BCR 8 19*03e525c6SSricharan Ramabadhran #define GCC_DDRSS_BCR 9 20*03e525c6SSricharan Ramabadhran #define GCC_PRNG_BCR 10 21*03e525c6SSricharan Ramabadhran #define GCC_BOOT_ROM_BCR 11 22*03e525c6SSricharan Ramabadhran #define GCC_NSS_BCR 12 23*03e525c6SSricharan Ramabadhran #define GCC_MDIO_BCR 13 24*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY0_BCR 14 25*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY1_BCR 15 26*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY2_BCR 16 27*03e525c6SSricharan Ramabadhran #define GCC_WCSS_BCR 17 28*03e525c6SSricharan Ramabadhran #define GCC_SEC_CTRL_BCR 19 29*03e525c6SSricharan Ramabadhran #define GCC_TME_SEC_BUS_BCR 20 30*03e525c6SSricharan Ramabadhran #define GCC_ADSS_BCR 21 31*03e525c6SSricharan Ramabadhran #define GCC_LPASS_BCR 22 32*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_BCR 23 33*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_LINK_DOWN_BCR 24 34*03e525c6SSricharan Ramabadhran #define GCC_PCIE0PHY_PHY_BCR 25 35*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_PHY_BCR 26 36*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_BCR 27 37*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_LINK_DOWN_BCR 28 38*03e525c6SSricharan Ramabadhran #define GCC_PCIE1PHY_PHY_BCR 29 39*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_PHY_BCR 30 40*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_BCR 31 41*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_LINK_DOWN_BCR 32 42*03e525c6SSricharan Ramabadhran #define GCC_PCIE2PHY_PHY_BCR 33 43*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_PHY_BCR 34 44*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_BCR 35 45*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_LINK_DOWN_BCR 36 46*03e525c6SSricharan Ramabadhran #define GCC_PCIE3PHY_PHY_BCR 37 47*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_PHY_BCR 38 48*03e525c6SSricharan Ramabadhran #define GCC_USB_BCR 39 49*03e525c6SSricharan Ramabadhran #define GCC_QUSB2_0_PHY_BCR 40 50*03e525c6SSricharan Ramabadhran #define GCC_USB0_PHY_BCR 41 51*03e525c6SSricharan Ramabadhran #define GCC_USB3PHY_0_PHY_BCR 42 52*03e525c6SSricharan Ramabadhran #define GCC_QDSS_BCR 43 53*03e525c6SSricharan Ramabadhran #define GCC_SNOC_BCR 44 54*03e525c6SSricharan Ramabadhran #define GCC_ANOC_BCR 45 55*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BCR 46 56*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT0_BCR 47 57*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT1_BCR 48 58*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT2_BCR 49 59*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT3_BCR 50 60*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT4_BCR 51 61*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT5_BCR 52 62*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT6_BCR 53 63*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT7_BCR 54 64*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT8_BCR 55 65*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT9_BCR 56 66*03e525c6SSricharan Ramabadhran #define GCC_QPIC_BCR 57 67*03e525c6SSricharan Ramabadhran #define GCC_SDCC_BCR 58 68*03e525c6SSricharan Ramabadhran #define GCC_DCC_BCR 59 69*03e525c6SSricharan Ramabadhran #define GCC_SPDM_BCR 60 70*03e525c6SSricharan Ramabadhran #define GCC_MPM_BCR 61 71*03e525c6SSricharan Ramabadhran #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 62 72*03e525c6SSricharan Ramabadhran #define GCC_RBCPR_BCR 63 73*03e525c6SSricharan Ramabadhran #define GCC_CMN_BLK_BCR 64 74*03e525c6SSricharan Ramabadhran #define GCC_TCSR_BCR 65 75*03e525c6SSricharan Ramabadhran #define GCC_TLMM_BCR 66 76*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_AHB_MST_ARES 67 77*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_CORE_ARES 68 78*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_2X_CORE_ARES 69 79*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_SLEEP_ARES 70 80*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_AHB_SLV_ARES 71 81*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_I2C0_ARES 72 82*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_UART0_ARES 73 83*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_I2C1_ARES 74 84*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_UART1_ARES 75 85*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_SPI0_ARES 76 86*03e525c6SSricharan Ramabadhran #define GCC_QUPV3_SPI1_ARES 77 87*03e525c6SSricharan Ramabadhran #define GCC_DEBUG_ARES 78 88*03e525c6SSricharan Ramabadhran #define GCC_GP1_ARES 79 89*03e525c6SSricharan Ramabadhran #define GCC_GP2_ARES 80 90*03e525c6SSricharan Ramabadhran #define GCC_GP3_ARES 81 91*03e525c6SSricharan Ramabadhran #define GCC_IMEM_AXI_ARES 82 92*03e525c6SSricharan Ramabadhran #define GCC_IMEM_CFG_AHB_ARES 83 93*03e525c6SSricharan Ramabadhran #define GCC_TME_ARES 84 94*03e525c6SSricharan Ramabadhran #define GCC_TME_TS_ARES 85 95*03e525c6SSricharan Ramabadhran #define GCC_TME_SLOW_ARES 86 96*03e525c6SSricharan Ramabadhran #define GCC_TME_RTC_TOGGLE_ARES 87 97*03e525c6SSricharan Ramabadhran #define GCC_TIC_ARES 88 98*03e525c6SSricharan Ramabadhran #define GCC_PRNG_AHB_ARES 89 99*03e525c6SSricharan Ramabadhran #define GCC_BOOT_ROM_AHB_ARES 90 100*03e525c6SSricharan Ramabadhran #define GCC_NSSNOC_ATB_ARES 91 101*03e525c6SSricharan Ramabadhran #define GCC_NSS_TS_ARES 92 102*03e525c6SSricharan Ramabadhran #define GCC_NSSNOC_QOSGEN_REF_ARES 93 103*03e525c6SSricharan Ramabadhran #define GCC_NSSNOC_TIMEOUT_REF_ARES 94 104*03e525c6SSricharan Ramabadhran #define GCC_NSSNOC_MEMNOC_ARES 95 105*03e525c6SSricharan Ramabadhran #define GCC_NSSNOC_SNOC_ARES 96 106*03e525c6SSricharan Ramabadhran #define GCC_NSSCFG_ARES 97 107*03e525c6SSricharan Ramabadhran #define GCC_NSSNOC_NSSCC_ARES 98 108*03e525c6SSricharan Ramabadhran #define GCC_NSSCC_ARES 99 109*03e525c6SSricharan Ramabadhran #define GCC_MDIO_AHB_ARES 100 110*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY0_SYS_ARES 101 111*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY0_AHB_ARES 102 112*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY1_SYS_ARES 103 113*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY1_AHB_ARES 104 114*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY2_SYS_ARES 105 115*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY2_AHB_ARES 106 116*03e525c6SSricharan Ramabadhran #define GCC_NSSNOC_XO_DCD_ARES 107 117*03e525c6SSricharan Ramabadhran #define GCC_NSSNOC_SNOC_1_ARES 108 118*03e525c6SSricharan Ramabadhran #define GCC_NSSNOC_PCNOC_1_ARES 109 119*03e525c6SSricharan Ramabadhran #define GCC_NSSNOC_MEMNOC_1_ARES 110 120*03e525c6SSricharan Ramabadhran #define GCC_DDRSS_ATB_ARES 111 121*03e525c6SSricharan Ramabadhran #define GCC_DDRSS_AHB_ARES 112 122*03e525c6SSricharan Ramabadhran #define GCC_GEMNOC_AHB_ARES 113 123*03e525c6SSricharan Ramabadhran #define GCC_GEMNOC_Q6_AXI_ARES 114 124*03e525c6SSricharan Ramabadhran #define GCC_GEMNOC_NSSNOC_ARES 115 125*03e525c6SSricharan Ramabadhran #define GCC_GEMNOC_SNOC_ARES 116 126*03e525c6SSricharan Ramabadhran #define GCC_GEMNOC_APSS_ARES 117 127*03e525c6SSricharan Ramabadhran #define GCC_GEMNOC_QOSGEN_EXTREF_ARES 118 128*03e525c6SSricharan Ramabadhran #define GCC_GEMNOC_TS_ARES 119 129*03e525c6SSricharan Ramabadhran #define GCC_DDRSS_SMS_SLOW_ARES 120 130*03e525c6SSricharan Ramabadhran #define GCC_GEMNOC_CNOC_ARES 121 131*03e525c6SSricharan Ramabadhran #define GCC_GEMNOC_XO_DBG_ARES 122 132*03e525c6SSricharan Ramabadhran #define GCC_GEMNOC_ANOC_ARES 123 133*03e525c6SSricharan Ramabadhran #define GCC_DDRSS_LLCC_ATB_ARES 124 134*03e525c6SSricharan Ramabadhran #define GCC_LLCC_TPDM_CFG_ARES 125 135*03e525c6SSricharan Ramabadhran #define GCC_TME_BUS_ARES 126 136*03e525c6SSricharan Ramabadhran #define GCC_SEC_CTRL_ACC_ARES 127 137*03e525c6SSricharan Ramabadhran #define GCC_SEC_CTRL_ARES 128 138*03e525c6SSricharan Ramabadhran #define GCC_SEC_CTRL_SENSE_ARES 129 139*03e525c6SSricharan Ramabadhran #define GCC_SEC_CTRL_AHB_ARES 130 140*03e525c6SSricharan Ramabadhran #define GCC_SEC_CTRL_BOOT_ROM_PATCH_ARES 131 141*03e525c6SSricharan Ramabadhran #define GCC_ADSS_PWM_ARES 132 142*03e525c6SSricharan Ramabadhran #define GCC_TME_ATB_ARES 133 143*03e525c6SSricharan Ramabadhran #define GCC_TME_DBGAPB_ARES 134 144*03e525c6SSricharan Ramabadhran #define GCC_TME_DEBUG_ARES 135 145*03e525c6SSricharan Ramabadhran #define GCC_TME_AT_ARES 136 146*03e525c6SSricharan Ramabadhran #define GCC_TME_APB_ARES 137 147*03e525c6SSricharan Ramabadhran #define GCC_TME_DMI_DBG_HS_ARES 138 148*03e525c6SSricharan Ramabadhran #define GCC_APSS_AHB_ARES 139 149*03e525c6SSricharan Ramabadhran #define GCC_APSS_AXI_ARES 140 150*03e525c6SSricharan Ramabadhran #define GCC_CPUSS_TRIG_ARES 141 151*03e525c6SSricharan Ramabadhran #define GCC_APSS_DBG_ARES 142 152*03e525c6SSricharan Ramabadhran #define GCC_APSS_TS_ARES 143 153*03e525c6SSricharan Ramabadhran #define GCC_APSS_ATB_ARES 144 154*03e525c6SSricharan Ramabadhran #define GCC_Q6_AXIM_ARES 145 155*03e525c6SSricharan Ramabadhran #define GCC_Q6_AXIS_ARES 146 156*03e525c6SSricharan Ramabadhran #define GCC_Q6_AHB_ARES 147 157*03e525c6SSricharan Ramabadhran #define GCC_Q6_AHB_S_ARES 148 158*03e525c6SSricharan Ramabadhran #define GCC_Q6SS_ATBM_ARES 149 159*03e525c6SSricharan Ramabadhran #define GCC_Q6_TSCTR_1TO2_ARES 150 160*03e525c6SSricharan Ramabadhran #define GCC_Q6SS_PCLKDBG_ARES 151 161*03e525c6SSricharan Ramabadhran #define GCC_Q6SS_TRIG_ARES 152 162*03e525c6SSricharan Ramabadhran #define GCC_Q6SS_BOOT_CBCR_ARES 153 163*03e525c6SSricharan Ramabadhran #define GCC_WCSS_DBG_IFC_APB_ARES 154 164*03e525c6SSricharan Ramabadhran #define GCC_WCSS_DBG_IFC_ATB_ARES 155 165*03e525c6SSricharan Ramabadhran #define GCC_WCSS_DBG_IFC_NTS_ARES 156 166*03e525c6SSricharan Ramabadhran #define GCC_WCSS_DBG_IFC_DAPBUS_ARES 157 167*03e525c6SSricharan Ramabadhran #define GCC_WCSS_DBG_IFC_APB_BDG_ARES 158 168*03e525c6SSricharan Ramabadhran #define GCC_WCSS_DBG_IFC_NTS_BDG_ARES 159 169*03e525c6SSricharan Ramabadhran #define GCC_WCSS_DBG_IFC_DAPBUS_BDG_ARES 160 170*03e525c6SSricharan Ramabadhran #define GCC_WCSS_ECAHB_ARES 161 171*03e525c6SSricharan Ramabadhran #define GCC_WCSS_ACMT_ARES 162 172*03e525c6SSricharan Ramabadhran #define GCC_WCSS_AHB_S_ARES 163 173*03e525c6SSricharan Ramabadhran #define GCC_WCSS_AXI_M_ARES 164 174*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_WAPSS_ARES 165 175*03e525c6SSricharan Ramabadhran #define GCC_SNOC_WAPSS_ARES 166 176*03e525c6SSricharan Ramabadhran #define GCC_LPASS_SWAY_ARES 167 177*03e525c6SSricharan Ramabadhran #define GCC_LPASS_CORE_AXIM_ARES 168 178*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AHB_ARES 169 179*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AXI_M_ARES 170 180*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AXI_S_ARES 171 181*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AXI_S_BRIDGE_ARES 172 182*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_PIPE_ARES 173 183*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AUX_ARES 174 184*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AHB_ARES 175 185*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AXI_M_ARES 176 186*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AXI_S_ARES 177 187*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AXI_S_BRIDGE_ARES 178 188*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_PIPE_ARES 179 189*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AUX_ARES 180 190*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AHB_ARES 181 191*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AXI_M_ARES 182 192*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AXI_S_ARES 183 193*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AXI_S_BRIDGE_ARES 184 194*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_PIPE_ARES 185 195*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AUX_ARES 186 196*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AHB_ARES 187 197*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AXI_M_ARES 188 198*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AXI_S_ARES 189 199*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AXI_S_BRIDGE_ARES 190 200*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_PIPE_ARES 191 201*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AUX_ARES 192 202*03e525c6SSricharan Ramabadhran #define GCC_USB0_MASTER_ARES 193 203*03e525c6SSricharan Ramabadhran #define GCC_USB0_AUX_ARES 194 204*03e525c6SSricharan Ramabadhran #define GCC_USB0_MOCK_UTMI_ARES 195 205*03e525c6SSricharan Ramabadhran #define GCC_USB0_PIPE_ARES 196 206*03e525c6SSricharan Ramabadhran #define GCC_USB0_SLEEP_ARES 197 207*03e525c6SSricharan Ramabadhran #define GCC_USB0_PHY_CFG_AHB_ARES 198 208*03e525c6SSricharan Ramabadhran #define GCC_QDSS_AT_ARES 199 209*03e525c6SSricharan Ramabadhran #define GCC_QDSS_STM_ARES 200 210*03e525c6SSricharan Ramabadhran #define GCC_QDSS_TRACECLKIN_ARES 201 211*03e525c6SSricharan Ramabadhran #define GCC_QDSS_TSCTR_DIV2_ARES 202 212*03e525c6SSricharan Ramabadhran #define GCC_QDSS_TSCTR_DIV3_ARES 203 213*03e525c6SSricharan Ramabadhran #define GCC_QDSS_TSCTR_DIV4_ARES 204 214*03e525c6SSricharan Ramabadhran #define GCC_QDSS_TSCTR_DIV8_ARES 205 215*03e525c6SSricharan Ramabadhran #define GCC_QDSS_TSCTR_DIV16_ARES 206 216*03e525c6SSricharan Ramabadhran #define GCC_QDSS_DAP_ARES 207 217*03e525c6SSricharan Ramabadhran #define GCC_QDSS_APB2JTAG_ARES 208 218*03e525c6SSricharan Ramabadhran #define GCC_QDSS_ETR_USB_ARES 209 219*03e525c6SSricharan Ramabadhran #define GCC_QDSS_DAP_AHB_ARES 210 220*03e525c6SSricharan Ramabadhran #define GCC_QDSS_CFG_AHB_ARES 211 221*03e525c6SSricharan Ramabadhran #define GCC_QDSS_EUD_AT_ARES 212 222*03e525c6SSricharan Ramabadhran #define GCC_QDSS_TS_ARES 213 223*03e525c6SSricharan Ramabadhran #define GCC_QDSS_USB_ARES 214 224*03e525c6SSricharan Ramabadhran #define GCC_SYS_NOC_AXI_ARES 215 225*03e525c6SSricharan Ramabadhran #define GCC_SNOC_QOSGEN_EXTREF_ARES 216 226*03e525c6SSricharan Ramabadhran #define GCC_CNOC_LPASS_CFG_ARES 217 227*03e525c6SSricharan Ramabadhran #define GCC_SYS_NOC_AT_ARES 218 228*03e525c6SSricharan Ramabadhran #define GCC_SNOC_PCNOC_AHB_ARES 219 229*03e525c6SSricharan Ramabadhran #define GCC_SNOC_TME_ARES 220 230*03e525c6SSricharan Ramabadhran #define GCC_SNOC_XO_DCD_ARES 221 231*03e525c6SSricharan Ramabadhran #define GCC_SNOC_TS_ARES 222 232*03e525c6SSricharan Ramabadhran #define GCC_ANOC0_AXI_ARES 223 233*03e525c6SSricharan Ramabadhran #define GCC_ANOC_PCIE0_1LANE_M_ARES 224 234*03e525c6SSricharan Ramabadhran #define GCC_ANOC_PCIE2_2LANE_M_ARES 225 235*03e525c6SSricharan Ramabadhran #define GCC_ANOC_PCIE1_1LANE_M_ARES 226 236*03e525c6SSricharan Ramabadhran #define GCC_ANOC_PCIE3_2LANE_M_ARES 227 237*03e525c6SSricharan Ramabadhran #define GCC_ANOC_PCNOC_AHB_ARES 228 238*03e525c6SSricharan Ramabadhran #define GCC_ANOC_QOSGEN_EXTREF_ARES 229 239*03e525c6SSricharan Ramabadhran #define GCC_ANOC_XO_DCD_ARES 230 240*03e525c6SSricharan Ramabadhran #define GCC_SNOC_XO_DBG_ARES 231 241*03e525c6SSricharan Ramabadhran #define GCC_AGGRNOC_ATB_ARES 232 242*03e525c6SSricharan Ramabadhran #define GCC_AGGRNOC_TS_ARES 233 243*03e525c6SSricharan Ramabadhran #define GCC_USB0_EUD_AT_ARES 234 244*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_TIC_ARES 235 245*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_AHB_ARES 236 246*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_XO_DBG_ARES 237 247*03e525c6SSricharan Ramabadhran #define GCC_SNOC_LPASS_ARES 238 248*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_AT_ARES 239 249*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_XO_DCD_ARES 240 250*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_TS_ARES 241 251*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT0_AHB_ARES 242 252*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT1_AHB_ARES 243 253*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT2_AHB_ARES 244 254*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT3_AHB_ARES 245 255*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT4_AHB_ARES 246 256*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT5_AHB_ARES 247 257*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT6_AHB_ARES 248 258*03e525c6SSricharan Ramabadhran #define GCC_PCNOC_BUS_TIMEOUT7_AHB_ARES 249 259*03e525c6SSricharan Ramabadhran #define GCC_Q6_AXIM_RESET 250 260*03e525c6SSricharan Ramabadhran #define GCC_Q6_AXIS_RESET 251 261*03e525c6SSricharan Ramabadhran #define GCC_Q6_AHB_S_RESET 252 262*03e525c6SSricharan Ramabadhran #define GCC_Q6_AHB_RESET 253 263*03e525c6SSricharan Ramabadhran #define GCC_Q6SS_DBG_RESET 254 264*03e525c6SSricharan Ramabadhran #define GCC_WCSS_ECAHB_RESET 255 265*03e525c6SSricharan Ramabadhran #define GCC_WCSS_DBG_BDG_RESET 256 266*03e525c6SSricharan Ramabadhran #define GCC_WCSS_DBG_RESET 257 267*03e525c6SSricharan Ramabadhran #define GCC_WCSS_AXI_M_RESET 258 268*03e525c6SSricharan Ramabadhran #define GCC_WCSS_AHB_S_RESET 259 269*03e525c6SSricharan Ramabadhran #define GCC_WCSS_ACMT_RESET 260 270*03e525c6SSricharan Ramabadhran #define GCC_WCSSAON_RESET 261 271*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_PIPE_RESET 262 272*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_CORE_STICKY_RESET 263 273*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AXI_S_STICKY_RESET 264 274*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AXI_S_RESET 265 275*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AXI_M_STICKY_RESET 266 276*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AXI_M_RESET 267 277*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AUX_RESET 268 278*03e525c6SSricharan Ramabadhran #define GCC_PCIE0_AHB_RESET 269 279*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_PIPE_RESET 270 280*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_CORE_STICKY_RESET 271 281*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AXI_S_STICKY_RESET 272 282*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AXI_S_RESET 273 283*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AXI_M_STICKY_RESET 274 284*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AXI_M_RESET 275 285*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AUX_RESET 276 286*03e525c6SSricharan Ramabadhran #define GCC_PCIE1_AHB_RESET 277 287*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_PIPE_RESET 278 288*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_CORE_STICKY_RESET 279 289*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AXI_S_STICKY_RESET 280 290*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AXI_S_RESET 281 291*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AXI_M_STICKY_RESET 282 292*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AXI_M_RESET 283 293*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AUX_RESET 284 294*03e525c6SSricharan Ramabadhran #define GCC_PCIE2_AHB_RESET 285 295*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_PIPE_RESET 286 296*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_CORE_STICKY_RESET 287 297*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AXI_S_STICKY_RESET 288 298*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AXI_S_RESET 289 299*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AXI_M_STICKY_RESET 290 300*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AXI_M_RESET 291 301*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AUX_RESET 292 302*03e525c6SSricharan Ramabadhran #define GCC_PCIE3_AHB_RESET 293 303*03e525c6SSricharan Ramabadhran #define GCC_NSS_PARTIAL_RESET 294 304*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY0_XPCS_ARES 295 305*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY1_XPCS_ARES 296 306*03e525c6SSricharan Ramabadhran #define GCC_UNIPHY2_XPCS_ARES 297 307*03e525c6SSricharan Ramabadhran #define GCC_USB1_BCR 298 308*03e525c6SSricharan Ramabadhran #define GCC_QUSB2_1_PHY_BCR 299 309*03e525c6SSricharan Ramabadhran 310*03e525c6SSricharan Ramabadhran #endif 311