1c9ccf71fSAndy Shevchenko // SPDX-License-Identifier: GPL-2.0 2c9ccf71fSAndy Shevchenko /* 3c9ccf71fSAndy Shevchenko * Intel Tiger Lake PCH pinctrl/GPIO driver 4c9ccf71fSAndy Shevchenko * 5cd0a3237SMika Westerberg * Copyright (C) 2019 - 2020, Intel Corporation 6c9ccf71fSAndy Shevchenko * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7c9ccf71fSAndy Shevchenko * Mika Westerberg <mika.westerberg@linux.intel.com> 8c9ccf71fSAndy Shevchenko */ 9c9ccf71fSAndy Shevchenko 10c9ccf71fSAndy Shevchenko #include <linux/mod_devicetable.h> 11c9ccf71fSAndy Shevchenko #include <linux/module.h> 12c9ccf71fSAndy Shevchenko #include <linux/platform_device.h> 13*ee4c71f5SAndy Shevchenko #include <linux/pm.h> 14c9ccf71fSAndy Shevchenko 15c9ccf71fSAndy Shevchenko #include <linux/pinctrl/pinctrl.h> 16c9ccf71fSAndy Shevchenko 17c9ccf71fSAndy Shevchenko #include "pinctrl-intel.h" 18c9ccf71fSAndy Shevchenko 19f72a8623SAndy Shevchenko #define TGL_LP_PAD_OWN 0x020 20cb8cc185SAndy Shevchenko #define TGL_LP_PADCFGLOCK 0x080 21cb8cc185SAndy Shevchenko #define TGL_LP_HOSTSW_OWN 0x0b0 22f72a8623SAndy Shevchenko #define TGL_LP_GPI_IS 0x100 23f72a8623SAndy Shevchenko #define TGL_LP_GPI_IE 0x120 24f72a8623SAndy Shevchenko 25f72a8623SAndy Shevchenko #define TGL_H_PAD_OWN 0x020 26f72a8623SAndy Shevchenko #define TGL_H_PADCFGLOCK 0x090 27cb8cc185SAndy Shevchenko #define TGL_H_HOSTSW_OWN 0x0c0 28f72a8623SAndy Shevchenko #define TGL_H_GPI_IS 0x100 29f72a8623SAndy Shevchenko #define TGL_H_GPI_IE 0x120 30c9ccf71fSAndy Shevchenko 31cd0a3237SMika Westerberg #define TGL_GPP(r, s, e, g) \ 32c9ccf71fSAndy Shevchenko { \ 33c9ccf71fSAndy Shevchenko .reg_num = (r), \ 34c9ccf71fSAndy Shevchenko .base = (s), \ 35c9ccf71fSAndy Shevchenko .size = ((e) - (s) + 1), \ 36cd0a3237SMika Westerberg .gpio_base = (g), \ 37c9ccf71fSAndy Shevchenko } 38c9ccf71fSAndy Shevchenko 39cb8cc185SAndy Shevchenko #define TGL_LP_COMMUNITY(b, s, e, g) \ 40f72a8623SAndy Shevchenko INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP) 41cb8cc185SAndy Shevchenko 42cb8cc185SAndy Shevchenko #define TGL_H_COMMUNITY(b, s, e, g) \ 43f72a8623SAndy Shevchenko INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_H) 44cb8cc185SAndy Shevchenko 45c9ccf71fSAndy Shevchenko /* Tiger Lake-LP */ 46cd0a3237SMika Westerberg static const struct pinctrl_pin_desc tgllp_pins[] = { 47c9ccf71fSAndy Shevchenko /* GPP_B */ 48c9ccf71fSAndy Shevchenko PINCTRL_PIN(0, "CORE_VID_0"), 49c9ccf71fSAndy Shevchenko PINCTRL_PIN(1, "CORE_VID_1"), 50c9ccf71fSAndy Shevchenko PINCTRL_PIN(2, "VRALERTB"), 51c9ccf71fSAndy Shevchenko PINCTRL_PIN(3, "CPU_GP_2"), 52c9ccf71fSAndy Shevchenko PINCTRL_PIN(4, "CPU_GP_3"), 53c9ccf71fSAndy Shevchenko PINCTRL_PIN(5, "ISH_I2C0_SDA"), 54c9ccf71fSAndy Shevchenko PINCTRL_PIN(6, "ISH_I2C0_SCL"), 55c9ccf71fSAndy Shevchenko PINCTRL_PIN(7, "ISH_I2C1_SDA"), 56c9ccf71fSAndy Shevchenko PINCTRL_PIN(8, "ISH_I2C1_SCL"), 57c9ccf71fSAndy Shevchenko PINCTRL_PIN(9, "I2C5_SDA"), 58c9ccf71fSAndy Shevchenko PINCTRL_PIN(10, "I2C5_SCL"), 59c9ccf71fSAndy Shevchenko PINCTRL_PIN(11, "PMCALERTB"), 60c9ccf71fSAndy Shevchenko PINCTRL_PIN(12, "SLP_S0B"), 61c9ccf71fSAndy Shevchenko PINCTRL_PIN(13, "PLTRSTB"), 62c9ccf71fSAndy Shevchenko PINCTRL_PIN(14, "SPKR"), 63c9ccf71fSAndy Shevchenko PINCTRL_PIN(15, "GSPI0_CS0B"), 64c9ccf71fSAndy Shevchenko PINCTRL_PIN(16, "GSPI0_CLK"), 65c9ccf71fSAndy Shevchenko PINCTRL_PIN(17, "GSPI0_MISO"), 66c9ccf71fSAndy Shevchenko PINCTRL_PIN(18, "GSPI0_MOSI"), 67c9ccf71fSAndy Shevchenko PINCTRL_PIN(19, "GSPI1_CS0B"), 68c9ccf71fSAndy Shevchenko PINCTRL_PIN(20, "GSPI1_CLK"), 69c9ccf71fSAndy Shevchenko PINCTRL_PIN(21, "GSPI1_MISO"), 70c9ccf71fSAndy Shevchenko PINCTRL_PIN(22, "GSPI1_MOSI"), 71c9ccf71fSAndy Shevchenko PINCTRL_PIN(23, "SML1ALERTB"), 72c9ccf71fSAndy Shevchenko PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"), 73c9ccf71fSAndy Shevchenko PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"), 74c9ccf71fSAndy Shevchenko /* GPP_T */ 75c9ccf71fSAndy Shevchenko PINCTRL_PIN(26, "I2C6_SDA"), 76c9ccf71fSAndy Shevchenko PINCTRL_PIN(27, "I2C6_SCL"), 77c9ccf71fSAndy Shevchenko PINCTRL_PIN(28, "I2C7_SDA"), 78c9ccf71fSAndy Shevchenko PINCTRL_PIN(29, "I2C7_SCL"), 79c9ccf71fSAndy Shevchenko PINCTRL_PIN(30, "UART4_RXD"), 80c9ccf71fSAndy Shevchenko PINCTRL_PIN(31, "UART4_TXD"), 81c9ccf71fSAndy Shevchenko PINCTRL_PIN(32, "UART4_RTSB"), 82c9ccf71fSAndy Shevchenko PINCTRL_PIN(33, "UART4_CTSB"), 83c9ccf71fSAndy Shevchenko PINCTRL_PIN(34, "UART5_RXD"), 84c9ccf71fSAndy Shevchenko PINCTRL_PIN(35, "UART5_TXD"), 85c9ccf71fSAndy Shevchenko PINCTRL_PIN(36, "UART5_RTSB"), 86c9ccf71fSAndy Shevchenko PINCTRL_PIN(37, "UART5_CTSB"), 87c9ccf71fSAndy Shevchenko PINCTRL_PIN(38, "UART6_RXD"), 88c9ccf71fSAndy Shevchenko PINCTRL_PIN(39, "UART6_TXD"), 89c9ccf71fSAndy Shevchenko PINCTRL_PIN(40, "UART6_RTSB"), 90c9ccf71fSAndy Shevchenko PINCTRL_PIN(41, "UART6_CTSB"), 91c9ccf71fSAndy Shevchenko /* GPP_A */ 92c9ccf71fSAndy Shevchenko PINCTRL_PIN(42, "ESPI_IO_0"), 93c9ccf71fSAndy Shevchenko PINCTRL_PIN(43, "ESPI_IO_1"), 94c9ccf71fSAndy Shevchenko PINCTRL_PIN(44, "ESPI_IO_2"), 95c9ccf71fSAndy Shevchenko PINCTRL_PIN(45, "ESPI_IO_3"), 96c9ccf71fSAndy Shevchenko PINCTRL_PIN(46, "ESPI_CSB"), 97c9ccf71fSAndy Shevchenko PINCTRL_PIN(47, "ESPI_CLK"), 98c9ccf71fSAndy Shevchenko PINCTRL_PIN(48, "ESPI_RESETB"), 99c9ccf71fSAndy Shevchenko PINCTRL_PIN(49, "I2S2_SCLK"), 100c9ccf71fSAndy Shevchenko PINCTRL_PIN(50, "I2S2_SFRM"), 101c9ccf71fSAndy Shevchenko PINCTRL_PIN(51, "I2S2_TXD"), 102c9ccf71fSAndy Shevchenko PINCTRL_PIN(52, "I2S2_RXD"), 103c9ccf71fSAndy Shevchenko PINCTRL_PIN(53, "PMC_I2C_SDA"), 104c9ccf71fSAndy Shevchenko PINCTRL_PIN(54, "SATAXPCIE_1"), 105c9ccf71fSAndy Shevchenko PINCTRL_PIN(55, "PMC_I2C_SCL"), 106c9ccf71fSAndy Shevchenko PINCTRL_PIN(56, "USB2_OCB_1"), 107c9ccf71fSAndy Shevchenko PINCTRL_PIN(57, "USB2_OCB_2"), 108c9ccf71fSAndy Shevchenko PINCTRL_PIN(58, "USB2_OCB_3"), 109c9ccf71fSAndy Shevchenko PINCTRL_PIN(59, "DDSP_HPD_C"), 110c9ccf71fSAndy Shevchenko PINCTRL_PIN(60, "DDSP_HPD_B"), 111c9ccf71fSAndy Shevchenko PINCTRL_PIN(61, "DDSP_HPD_1"), 112c9ccf71fSAndy Shevchenko PINCTRL_PIN(62, "DDSP_HPD_2"), 113c9ccf71fSAndy Shevchenko PINCTRL_PIN(63, "GPPC_A_21"), 114c9ccf71fSAndy Shevchenko PINCTRL_PIN(64, "GPPC_A_22"), 115c9ccf71fSAndy Shevchenko PINCTRL_PIN(65, "I2S1_SCLK"), 116c9ccf71fSAndy Shevchenko PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), 117cd0a3237SMika Westerberg /* GPP_S */ 118cd0a3237SMika Westerberg PINCTRL_PIN(67, "SNDW0_CLK"), 119cd0a3237SMika Westerberg PINCTRL_PIN(68, "SNDW0_DATA"), 120cd0a3237SMika Westerberg PINCTRL_PIN(69, "SNDW1_CLK"), 121cd0a3237SMika Westerberg PINCTRL_PIN(70, "SNDW1_DATA"), 122cd0a3237SMika Westerberg PINCTRL_PIN(71, "SNDW2_CLK"), 123cd0a3237SMika Westerberg PINCTRL_PIN(72, "SNDW2_DATA"), 124cd0a3237SMika Westerberg PINCTRL_PIN(73, "SNDW3_CLK"), 125cd0a3237SMika Westerberg PINCTRL_PIN(74, "SNDW3_DATA"), 126cd0a3237SMika Westerberg /* GPP_H */ 127cd0a3237SMika Westerberg PINCTRL_PIN(75, "GPPC_H_0"), 128cd0a3237SMika Westerberg PINCTRL_PIN(76, "GPPC_H_1"), 129cd0a3237SMika Westerberg PINCTRL_PIN(77, "GPPC_H_2"), 130cd0a3237SMika Westerberg PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"), 131cd0a3237SMika Westerberg PINCTRL_PIN(79, "I2C2_SDA"), 132cd0a3237SMika Westerberg PINCTRL_PIN(80, "I2C2_SCL"), 133cd0a3237SMika Westerberg PINCTRL_PIN(81, "I2C3_SDA"), 134cd0a3237SMika Westerberg PINCTRL_PIN(82, "I2C3_SCL"), 135cd0a3237SMika Westerberg PINCTRL_PIN(83, "I2C4_SDA"), 136cd0a3237SMika Westerberg PINCTRL_PIN(84, "I2C4_SCL"), 137cd0a3237SMika Westerberg PINCTRL_PIN(85, "SRCCLKREQB_4"), 138cd0a3237SMika Westerberg PINCTRL_PIN(86, "SRCCLKREQB_5"), 139cd0a3237SMika Westerberg PINCTRL_PIN(87, "M2_SKT2_CFG_0"), 140cd0a3237SMika Westerberg PINCTRL_PIN(88, "M2_SKT2_CFG_1"), 141cd0a3237SMika Westerberg PINCTRL_PIN(89, "M2_SKT2_CFG_2"), 142cd0a3237SMika Westerberg PINCTRL_PIN(90, "M2_SKT2_CFG_3"), 143cd0a3237SMika Westerberg PINCTRL_PIN(91, "DDPB_CTRLCLK"), 144cd0a3237SMika Westerberg PINCTRL_PIN(92, "DDPB_CTRLDATA"), 145cd0a3237SMika Westerberg PINCTRL_PIN(93, "CPU_C10_GATEB"), 146cd0a3237SMika Westerberg PINCTRL_PIN(94, "TIME_SYNC_0"), 147cd0a3237SMika Westerberg PINCTRL_PIN(95, "IMGCLKOUT_1"), 148cd0a3237SMika Westerberg PINCTRL_PIN(96, "IMGCLKOUT_2"), 149cd0a3237SMika Westerberg PINCTRL_PIN(97, "IMGCLKOUT_3"), 150cd0a3237SMika Westerberg PINCTRL_PIN(98, "IMGCLKOUT_4"), 151cd0a3237SMika Westerberg /* GPP_D */ 152cd0a3237SMika Westerberg PINCTRL_PIN(99, "ISH_GP_0"), 153cd0a3237SMika Westerberg PINCTRL_PIN(100, "ISH_GP_1"), 154cd0a3237SMika Westerberg PINCTRL_PIN(101, "ISH_GP_2"), 155cd0a3237SMika Westerberg PINCTRL_PIN(102, "ISH_GP_3"), 156cd0a3237SMika Westerberg PINCTRL_PIN(103, "IMGCLKOUT_0"), 157cd0a3237SMika Westerberg PINCTRL_PIN(104, "SRCCLKREQB_0"), 158cd0a3237SMika Westerberg PINCTRL_PIN(105, "SRCCLKREQB_1"), 159cd0a3237SMika Westerberg PINCTRL_PIN(106, "SRCCLKREQB_2"), 160cd0a3237SMika Westerberg PINCTRL_PIN(107, "SRCCLKREQB_3"), 161cd0a3237SMika Westerberg PINCTRL_PIN(108, "ISH_SPI_CSB"), 162cd0a3237SMika Westerberg PINCTRL_PIN(109, "ISH_SPI_CLK"), 163cd0a3237SMika Westerberg PINCTRL_PIN(110, "ISH_SPI_MISO"), 164cd0a3237SMika Westerberg PINCTRL_PIN(111, "ISH_SPI_MOSI"), 165cd0a3237SMika Westerberg PINCTRL_PIN(112, "ISH_UART0_RXD"), 166cd0a3237SMika Westerberg PINCTRL_PIN(113, "ISH_UART0_TXD"), 167cd0a3237SMika Westerberg PINCTRL_PIN(114, "ISH_UART0_RTSB"), 168cd0a3237SMika Westerberg PINCTRL_PIN(115, "ISH_UART0_CTSB"), 169cd0a3237SMika Westerberg PINCTRL_PIN(116, "ISH_GP_4"), 170cd0a3237SMika Westerberg PINCTRL_PIN(117, "ISH_GP_5"), 171cd0a3237SMika Westerberg PINCTRL_PIN(118, "I2S_MCLK1_OUT"), 172cd0a3237SMika Westerberg PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"), 173cd0a3237SMika Westerberg /* GPP_U */ 174cd0a3237SMika Westerberg PINCTRL_PIN(120, "UART3_RXD"), 175cd0a3237SMika Westerberg PINCTRL_PIN(121, "UART3_TXD"), 176cd0a3237SMika Westerberg PINCTRL_PIN(122, "UART3_RTSB"), 177cd0a3237SMika Westerberg PINCTRL_PIN(123, "UART3_CTSB"), 178cd0a3237SMika Westerberg PINCTRL_PIN(124, "GSPI3_CS0B"), 179cd0a3237SMika Westerberg PINCTRL_PIN(125, "GSPI3_CLK"), 180cd0a3237SMika Westerberg PINCTRL_PIN(126, "GSPI3_MISO"), 181cd0a3237SMika Westerberg PINCTRL_PIN(127, "GSPI3_MOSI"), 182cd0a3237SMika Westerberg PINCTRL_PIN(128, "GSPI4_CS0B"), 183cd0a3237SMika Westerberg PINCTRL_PIN(129, "GSPI4_CLK"), 184cd0a3237SMika Westerberg PINCTRL_PIN(130, "GSPI4_MISO"), 185cd0a3237SMika Westerberg PINCTRL_PIN(131, "GSPI4_MOSI"), 186cd0a3237SMika Westerberg PINCTRL_PIN(132, "GSPI5_CS0B"), 187cd0a3237SMika Westerberg PINCTRL_PIN(133, "GSPI5_CLK"), 188cd0a3237SMika Westerberg PINCTRL_PIN(134, "GSPI5_MISO"), 189cd0a3237SMika Westerberg PINCTRL_PIN(135, "GSPI5_MOSI"), 190cd0a3237SMika Westerberg PINCTRL_PIN(136, "GSPI6_CS0B"), 191cd0a3237SMika Westerberg PINCTRL_PIN(137, "GSPI6_CLK"), 192cd0a3237SMika Westerberg PINCTRL_PIN(138, "GSPI6_MISO"), 193cd0a3237SMika Westerberg PINCTRL_PIN(139, "GSPI6_MOSI"), 194cd0a3237SMika Westerberg PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"), 195cd0a3237SMika Westerberg PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"), 196cd0a3237SMika Westerberg PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"), 197cd0a3237SMika Westerberg PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"), 198cd0a3237SMika Westerberg /* vGPIO */ 199cd0a3237SMika Westerberg PINCTRL_PIN(144, "CNV_BTEN"), 200cd0a3237SMika Westerberg PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"), 201cd0a3237SMika Westerberg PINCTRL_PIN(146, "CNV_BT_IF_SELECT"), 202cd0a3237SMika Westerberg PINCTRL_PIN(147, "vCNV_BT_UART_TXD"), 203cd0a3237SMika Westerberg PINCTRL_PIN(148, "vCNV_BT_UART_RXD"), 204cd0a3237SMika Westerberg PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"), 205cd0a3237SMika Westerberg PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"), 206cd0a3237SMika Westerberg PINCTRL_PIN(151, "vCNV_MFUART1_TXD"), 207cd0a3237SMika Westerberg PINCTRL_PIN(152, "vCNV_MFUART1_RXD"), 208cd0a3237SMika Westerberg PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"), 209cd0a3237SMika Westerberg PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"), 210cd0a3237SMika Westerberg PINCTRL_PIN(155, "vUART0_TXD"), 211cd0a3237SMika Westerberg PINCTRL_PIN(156, "vUART0_RXD"), 212cd0a3237SMika Westerberg PINCTRL_PIN(157, "vUART0_CTS_B"), 213cd0a3237SMika Westerberg PINCTRL_PIN(158, "vUART0_RTS_B"), 214cd0a3237SMika Westerberg PINCTRL_PIN(159, "vISH_UART0_TXD"), 215cd0a3237SMika Westerberg PINCTRL_PIN(160, "vISH_UART0_RXD"), 216cd0a3237SMika Westerberg PINCTRL_PIN(161, "vISH_UART0_CTS_B"), 217cd0a3237SMika Westerberg PINCTRL_PIN(162, "vISH_UART0_RTS_B"), 218cd0a3237SMika Westerberg PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"), 219cd0a3237SMika Westerberg PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"), 220cd0a3237SMika Westerberg PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"), 221cd0a3237SMika Westerberg PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"), 222cd0a3237SMika Westerberg PINCTRL_PIN(167, "vI2S2_SCLK"), 223cd0a3237SMika Westerberg PINCTRL_PIN(168, "vI2S2_SFRM"), 224cd0a3237SMika Westerberg PINCTRL_PIN(169, "vI2S2_TXD"), 225cd0a3237SMika Westerberg PINCTRL_PIN(170, "vI2S2_RXD"), 226cd0a3237SMika Westerberg /* GPP_C */ 227cd0a3237SMika Westerberg PINCTRL_PIN(171, "SMBCLK"), 228cd0a3237SMika Westerberg PINCTRL_PIN(172, "SMBDATA"), 229cd0a3237SMika Westerberg PINCTRL_PIN(173, "SMBALERTB"), 230cd0a3237SMika Westerberg PINCTRL_PIN(174, "SML0CLK"), 231cd0a3237SMika Westerberg PINCTRL_PIN(175, "SML0DATA"), 232cd0a3237SMika Westerberg PINCTRL_PIN(176, "SML0ALERTB"), 233cd0a3237SMika Westerberg PINCTRL_PIN(177, "SML1CLK"), 234cd0a3237SMika Westerberg PINCTRL_PIN(178, "SML1DATA"), 235cd0a3237SMika Westerberg PINCTRL_PIN(179, "UART0_RXD"), 236cd0a3237SMika Westerberg PINCTRL_PIN(180, "UART0_TXD"), 237cd0a3237SMika Westerberg PINCTRL_PIN(181, "UART0_RTSB"), 238cd0a3237SMika Westerberg PINCTRL_PIN(182, "UART0_CTSB"), 239cd0a3237SMika Westerberg PINCTRL_PIN(183, "UART1_RXD"), 240cd0a3237SMika Westerberg PINCTRL_PIN(184, "UART1_TXD"), 241cd0a3237SMika Westerberg PINCTRL_PIN(185, "UART1_RTSB"), 242cd0a3237SMika Westerberg PINCTRL_PIN(186, "UART1_CTSB"), 243cd0a3237SMika Westerberg PINCTRL_PIN(187, "I2C0_SDA"), 244cd0a3237SMika Westerberg PINCTRL_PIN(188, "I2C0_SCL"), 245cd0a3237SMika Westerberg PINCTRL_PIN(189, "I2C1_SDA"), 246cd0a3237SMika Westerberg PINCTRL_PIN(190, "I2C1_SCL"), 247cd0a3237SMika Westerberg PINCTRL_PIN(191, "UART2_RXD"), 248cd0a3237SMika Westerberg PINCTRL_PIN(192, "UART2_TXD"), 249cd0a3237SMika Westerberg PINCTRL_PIN(193, "UART2_RTSB"), 250cd0a3237SMika Westerberg PINCTRL_PIN(194, "UART2_CTSB"), 251cd0a3237SMika Westerberg /* GPP_F */ 252cd0a3237SMika Westerberg PINCTRL_PIN(195, "CNV_BRI_DT"), 253cd0a3237SMika Westerberg PINCTRL_PIN(196, "CNV_BRI_RSP"), 254cd0a3237SMika Westerberg PINCTRL_PIN(197, "CNV_RGI_DT"), 255cd0a3237SMika Westerberg PINCTRL_PIN(198, "CNV_RGI_RSP"), 256cd0a3237SMika Westerberg PINCTRL_PIN(199, "CNV_RF_RESET_B"), 257cd0a3237SMika Westerberg PINCTRL_PIN(200, "GPPC_F_5"), 258cd0a3237SMika Westerberg PINCTRL_PIN(201, "CNV_PA_BLANKING"), 259cd0a3237SMika Westerberg PINCTRL_PIN(202, "GPPC_F_7"), 260cd0a3237SMika Westerberg PINCTRL_PIN(203, "I2S_MCLK2_INOUT"), 261cd0a3237SMika Westerberg PINCTRL_PIN(204, "BOOTMPC"), 262cd0a3237SMika Westerberg PINCTRL_PIN(205, "GPPC_F_10"), 263cd0a3237SMika Westerberg PINCTRL_PIN(206, "GPPC_F_11"), 264cd0a3237SMika Westerberg PINCTRL_PIN(207, "GSXDOUT"), 265cd0a3237SMika Westerberg PINCTRL_PIN(208, "GSXSLOAD"), 266cd0a3237SMika Westerberg PINCTRL_PIN(209, "GSXDIN"), 267cd0a3237SMika Westerberg PINCTRL_PIN(210, "GSXSRESETB"), 268cd0a3237SMika Westerberg PINCTRL_PIN(211, "GSXCLK"), 269cd0a3237SMika Westerberg PINCTRL_PIN(212, "GMII_MDC"), 270cd0a3237SMika Westerberg PINCTRL_PIN(213, "GMII_MDIO"), 271cd0a3237SMika Westerberg PINCTRL_PIN(214, "SRCCLKREQB_6"), 272cd0a3237SMika Westerberg PINCTRL_PIN(215, "EXT_PWR_GATEB"), 273cd0a3237SMika Westerberg PINCTRL_PIN(216, "EXT_PWR_GATE2B"), 274cd0a3237SMika Westerberg PINCTRL_PIN(217, "VNN_CTRL"), 275cd0a3237SMika Westerberg PINCTRL_PIN(218, "V1P05_CTRL"), 276cd0a3237SMika Westerberg PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"), 277cd0a3237SMika Westerberg /* HVCMOS */ 278cd0a3237SMika Westerberg PINCTRL_PIN(220, "L_BKLTEN"), 279cd0a3237SMika Westerberg PINCTRL_PIN(221, "L_BKLTCTL"), 280cd0a3237SMika Westerberg PINCTRL_PIN(222, "L_VDDEN"), 281cd0a3237SMika Westerberg PINCTRL_PIN(223, "SYS_PWROK"), 282cd0a3237SMika Westerberg PINCTRL_PIN(224, "SYS_RESETB"), 283cd0a3237SMika Westerberg PINCTRL_PIN(225, "MLK_RSTB"), 284cd0a3237SMika Westerberg /* GPP_E */ 285cd0a3237SMika Westerberg PINCTRL_PIN(226, "SATAXPCIE_0"), 286cd0a3237SMika Westerberg PINCTRL_PIN(227, "SPI1_IO_2"), 287cd0a3237SMika Westerberg PINCTRL_PIN(228, "SPI1_IO_3"), 288cd0a3237SMika Westerberg PINCTRL_PIN(229, "CPU_GP_0"), 289cd0a3237SMika Westerberg PINCTRL_PIN(230, "SATA_DEVSLP_0"), 290cd0a3237SMika Westerberg PINCTRL_PIN(231, "SATA_DEVSLP_1"), 291cd0a3237SMika Westerberg PINCTRL_PIN(232, "GPPC_E_6"), 292cd0a3237SMika Westerberg PINCTRL_PIN(233, "CPU_GP_1"), 293cd0a3237SMika Westerberg PINCTRL_PIN(234, "SPI1_CS1B"), 294cd0a3237SMika Westerberg PINCTRL_PIN(235, "USB2_OCB_0"), 295cd0a3237SMika Westerberg PINCTRL_PIN(236, "SPI1_CSB"), 296cd0a3237SMika Westerberg PINCTRL_PIN(237, "SPI1_CLK"), 297cd0a3237SMika Westerberg PINCTRL_PIN(238, "SPI1_MISO_IO_1"), 298cd0a3237SMika Westerberg PINCTRL_PIN(239, "SPI1_MOSI_IO_0"), 299cd0a3237SMika Westerberg PINCTRL_PIN(240, "DDSP_HPD_A"), 300cd0a3237SMika Westerberg PINCTRL_PIN(241, "ISH_GP_6"), 301cd0a3237SMika Westerberg PINCTRL_PIN(242, "ISH_GP_7"), 302cd0a3237SMika Westerberg PINCTRL_PIN(243, "GPPC_E_17"), 303cd0a3237SMika Westerberg PINCTRL_PIN(244, "DDP1_CTRLCLK"), 304cd0a3237SMika Westerberg PINCTRL_PIN(245, "DDP1_CTRLDATA"), 305cd0a3237SMika Westerberg PINCTRL_PIN(246, "DDP2_CTRLCLK"), 306cd0a3237SMika Westerberg PINCTRL_PIN(247, "DDP2_CTRLDATA"), 307cd0a3237SMika Westerberg PINCTRL_PIN(248, "DDPA_CTRLCLK"), 308cd0a3237SMika Westerberg PINCTRL_PIN(249, "DDPA_CTRLDATA"), 309cd0a3237SMika Westerberg PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"), 310cd0a3237SMika Westerberg /* JTAG */ 311cd0a3237SMika Westerberg PINCTRL_PIN(251, "JTAG_TDO"), 312cd0a3237SMika Westerberg PINCTRL_PIN(252, "JTAGX"), 313cd0a3237SMika Westerberg PINCTRL_PIN(253, "PRDYB"), 314cd0a3237SMika Westerberg PINCTRL_PIN(254, "PREQB"), 315cd0a3237SMika Westerberg PINCTRL_PIN(255, "CPU_TRSTB"), 316cd0a3237SMika Westerberg PINCTRL_PIN(256, "JTAG_TDI"), 317cd0a3237SMika Westerberg PINCTRL_PIN(257, "JTAG_TMS"), 318cd0a3237SMika Westerberg PINCTRL_PIN(258, "JTAG_TCK"), 319cd0a3237SMika Westerberg PINCTRL_PIN(259, "DBG_PMODE"), 320cd0a3237SMika Westerberg /* GPP_R */ 321cd0a3237SMika Westerberg PINCTRL_PIN(260, "HDA_BCLK"), 322cd0a3237SMika Westerberg PINCTRL_PIN(261, "HDA_SYNC"), 323cd0a3237SMika Westerberg PINCTRL_PIN(262, "HDA_SDO"), 324cd0a3237SMika Westerberg PINCTRL_PIN(263, "HDA_SDI_0"), 325cd0a3237SMika Westerberg PINCTRL_PIN(264, "HDA_RSTB"), 326cd0a3237SMika Westerberg PINCTRL_PIN(265, "HDA_SDI_1"), 327cd0a3237SMika Westerberg PINCTRL_PIN(266, "GPP_R_6"), 328cd0a3237SMika Westerberg PINCTRL_PIN(267, "GPP_R_7"), 329cd0a3237SMika Westerberg /* SPI */ 330cd0a3237SMika Westerberg PINCTRL_PIN(268, "SPI0_IO_2"), 331cd0a3237SMika Westerberg PINCTRL_PIN(269, "SPI0_IO_3"), 332cd0a3237SMika Westerberg PINCTRL_PIN(270, "SPI0_MOSI_IO_0"), 333cd0a3237SMika Westerberg PINCTRL_PIN(271, "SPI0_MISO_IO_1"), 334cd0a3237SMika Westerberg PINCTRL_PIN(272, "SPI0_TPM_CSB"), 335cd0a3237SMika Westerberg PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"), 336cd0a3237SMika Westerberg PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"), 337cd0a3237SMika Westerberg PINCTRL_PIN(275, "SPI0_CLK"), 338cd0a3237SMika Westerberg PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"), 339c9ccf71fSAndy Shevchenko }; 340c9ccf71fSAndy Shevchenko 341c9ccf71fSAndy Shevchenko static const struct intel_padgroup tgllp_community0_gpps[] = { 342cd0a3237SMika Westerberg TGL_GPP(0, 0, 25, 0), /* GPP_B */ 343cd0a3237SMika Westerberg TGL_GPP(1, 26, 41, 32), /* GPP_T */ 344cd0a3237SMika Westerberg TGL_GPP(2, 42, 66, 64), /* GPP_A */ 345c9ccf71fSAndy Shevchenko }; 346c9ccf71fSAndy Shevchenko 347c9ccf71fSAndy Shevchenko static const struct intel_padgroup tgllp_community1_gpps[] = { 348cd0a3237SMika Westerberg TGL_GPP(0, 67, 74, 96), /* GPP_S */ 349cd0a3237SMika Westerberg TGL_GPP(1, 75, 98, 128), /* GPP_H */ 350cd0a3237SMika Westerberg TGL_GPP(2, 99, 119, 160), /* GPP_D */ 351cd0a3237SMika Westerberg TGL_GPP(3, 120, 143, 192), /* GPP_U */ 352cd0a3237SMika Westerberg TGL_GPP(4, 144, 170, 224), /* vGPIO */ 353c9ccf71fSAndy Shevchenko }; 354c9ccf71fSAndy Shevchenko 355c9ccf71fSAndy Shevchenko static const struct intel_padgroup tgllp_community4_gpps[] = { 356cd0a3237SMika Westerberg TGL_GPP(0, 171, 194, 256), /* GPP_C */ 357cd0a3237SMika Westerberg TGL_GPP(1, 195, 219, 288), /* GPP_F */ 358d4b41f8bSAndy Shevchenko TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 359cd0a3237SMika Westerberg TGL_GPP(3, 226, 250, 320), /* GPP_E */ 360d4b41f8bSAndy Shevchenko TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 361c9ccf71fSAndy Shevchenko }; 362c9ccf71fSAndy Shevchenko 363c9ccf71fSAndy Shevchenko static const struct intel_padgroup tgllp_community5_gpps[] = { 364cd0a3237SMika Westerberg TGL_GPP(0, 260, 267, 352), /* GPP_R */ 365d4b41f8bSAndy Shevchenko TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ 366c9ccf71fSAndy Shevchenko }; 367c9ccf71fSAndy Shevchenko 368cd0a3237SMika Westerberg static const struct intel_community tgllp_communities[] = { 369cb8cc185SAndy Shevchenko TGL_LP_COMMUNITY(0, 0, 66, tgllp_community0_gpps), 370cb8cc185SAndy Shevchenko TGL_LP_COMMUNITY(1, 67, 170, tgllp_community1_gpps), 371cb8cc185SAndy Shevchenko TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps), 372cb8cc185SAndy Shevchenko TGL_LP_COMMUNITY(3, 260, 276, tgllp_community5_gpps), 373c9ccf71fSAndy Shevchenko }; 374c9ccf71fSAndy Shevchenko 375cd0a3237SMika Westerberg static const struct intel_pinctrl_soc_data tgllp_soc_data = { 376cd0a3237SMika Westerberg .pins = tgllp_pins, 377cd0a3237SMika Westerberg .npins = ARRAY_SIZE(tgllp_pins), 378cd0a3237SMika Westerberg .communities = tgllp_communities, 379cd0a3237SMika Westerberg .ncommunities = ARRAY_SIZE(tgllp_communities), 380c9ccf71fSAndy Shevchenko }; 381c9ccf71fSAndy Shevchenko 382653d9645SMika Westerberg /* Tiger Lake-H */ 383653d9645SMika Westerberg static const struct pinctrl_pin_desc tglh_pins[] = { 384653d9645SMika Westerberg /* GPP_A */ 385653d9645SMika Westerberg PINCTRL_PIN(0, "SPI0_IO_2"), 386653d9645SMika Westerberg PINCTRL_PIN(1, "SPI0_IO_3"), 387653d9645SMika Westerberg PINCTRL_PIN(2, "SPI0_MOSI_IO_0"), 388653d9645SMika Westerberg PINCTRL_PIN(3, "SPI0_MISO_IO_1"), 389653d9645SMika Westerberg PINCTRL_PIN(4, "SPI0_TPM_CSB"), 390653d9645SMika Westerberg PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"), 391653d9645SMika Westerberg PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"), 392653d9645SMika Westerberg PINCTRL_PIN(7, "SPI0_CLK"), 393653d9645SMika Westerberg PINCTRL_PIN(8, "ESPI_IO_0"), 394653d9645SMika Westerberg PINCTRL_PIN(9, "ESPI_IO_1"), 395653d9645SMika Westerberg PINCTRL_PIN(10, "ESPI_IO_2"), 396653d9645SMika Westerberg PINCTRL_PIN(11, "ESPI_IO_3"), 397653d9645SMika Westerberg PINCTRL_PIN(12, "ESPI_CS0B"), 398653d9645SMika Westerberg PINCTRL_PIN(13, "ESPI_CLK"), 399653d9645SMika Westerberg PINCTRL_PIN(14, "ESPI_RESETB"), 400653d9645SMika Westerberg PINCTRL_PIN(15, "ESPI_CS1B"), 401653d9645SMika Westerberg PINCTRL_PIN(16, "ESPI_CS2B"), 402653d9645SMika Westerberg PINCTRL_PIN(17, "ESPI_CS3B"), 403653d9645SMika Westerberg PINCTRL_PIN(18, "ESPI_ALERT0B"), 404653d9645SMika Westerberg PINCTRL_PIN(19, "ESPI_ALERT1B"), 405653d9645SMika Westerberg PINCTRL_PIN(20, "ESPI_ALERT2B"), 406653d9645SMika Westerberg PINCTRL_PIN(21, "ESPI_ALERT3B"), 407653d9645SMika Westerberg PINCTRL_PIN(22, "GPPC_A_14"), 408653d9645SMika Westerberg PINCTRL_PIN(23, "SPI0_CLK_LOOPBK"), 409653d9645SMika Westerberg PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"), 410653d9645SMika Westerberg /* GPP_R */ 411653d9645SMika Westerberg PINCTRL_PIN(25, "HDA_BCLK"), 412653d9645SMika Westerberg PINCTRL_PIN(26, "HDA_SYNC"), 413653d9645SMika Westerberg PINCTRL_PIN(27, "HDA_SDO"), 414653d9645SMika Westerberg PINCTRL_PIN(28, "HDA_SDI_0"), 415653d9645SMika Westerberg PINCTRL_PIN(29, "HDA_RSTB"), 416653d9645SMika Westerberg PINCTRL_PIN(30, "HDA_SDI_1"), 417653d9645SMika Westerberg PINCTRL_PIN(31, "GPP_R_6"), 418653d9645SMika Westerberg PINCTRL_PIN(32, "GPP_R_7"), 419653d9645SMika Westerberg PINCTRL_PIN(33, "GPP_R_8"), 420653d9645SMika Westerberg PINCTRL_PIN(34, "PCIE_LNK_DOWN"), 421653d9645SMika Westerberg PINCTRL_PIN(35, "ISH_UART0_RTSB"), 422653d9645SMika Westerberg PINCTRL_PIN(36, "SX_EXIT_HOLDOFFB"), 423653d9645SMika Westerberg PINCTRL_PIN(37, "CLKOUT_48"), 424653d9645SMika Westerberg PINCTRL_PIN(38, "ISH_GP_7"), 425653d9645SMika Westerberg PINCTRL_PIN(39, "ISH_GP_0"), 426653d9645SMika Westerberg PINCTRL_PIN(40, "ISH_GP_1"), 427653d9645SMika Westerberg PINCTRL_PIN(41, "ISH_GP_2"), 428653d9645SMika Westerberg PINCTRL_PIN(42, "ISH_GP_3"), 429653d9645SMika Westerberg PINCTRL_PIN(43, "ISH_GP_4"), 430653d9645SMika Westerberg PINCTRL_PIN(44, "ISH_GP_5"), 431653d9645SMika Westerberg /* GPP_B */ 432653d9645SMika Westerberg PINCTRL_PIN(45, "GSPI0_CS1B"), 433653d9645SMika Westerberg PINCTRL_PIN(46, "GSPI1_CS1B"), 434653d9645SMika Westerberg PINCTRL_PIN(47, "VRALERTB"), 435653d9645SMika Westerberg PINCTRL_PIN(48, "CPU_GP_2"), 436653d9645SMika Westerberg PINCTRL_PIN(49, "CPU_GP_3"), 437653d9645SMika Westerberg PINCTRL_PIN(50, "SRCCLKREQB_0"), 438653d9645SMika Westerberg PINCTRL_PIN(51, "SRCCLKREQB_1"), 439653d9645SMika Westerberg PINCTRL_PIN(52, "SRCCLKREQB_2"), 440653d9645SMika Westerberg PINCTRL_PIN(53, "SRCCLKREQB_3"), 441653d9645SMika Westerberg PINCTRL_PIN(54, "SRCCLKREQB_4"), 442653d9645SMika Westerberg PINCTRL_PIN(55, "SRCCLKREQB_5"), 443653d9645SMika Westerberg PINCTRL_PIN(56, "I2S_MCLK"), 444653d9645SMika Westerberg PINCTRL_PIN(57, "SLP_S0B"), 445653d9645SMika Westerberg PINCTRL_PIN(58, "PLTRSTB"), 446653d9645SMika Westerberg PINCTRL_PIN(59, "SPKR"), 447653d9645SMika Westerberg PINCTRL_PIN(60, "GSPI0_CS0B"), 448653d9645SMika Westerberg PINCTRL_PIN(61, "GSPI0_CLK"), 449653d9645SMika Westerberg PINCTRL_PIN(62, "GSPI0_MISO"), 450653d9645SMika Westerberg PINCTRL_PIN(63, "GSPI0_MOSI"), 451653d9645SMika Westerberg PINCTRL_PIN(64, "GSPI1_CS0B"), 452653d9645SMika Westerberg PINCTRL_PIN(65, "GSPI1_CLK"), 453653d9645SMika Westerberg PINCTRL_PIN(66, "GSPI1_MISO"), 454653d9645SMika Westerberg PINCTRL_PIN(67, "GSPI1_MOSI"), 455653d9645SMika Westerberg PINCTRL_PIN(68, "SML1ALERTB"), 456653d9645SMika Westerberg PINCTRL_PIN(69, "GSPI0_CLK_LOOPBK"), 457653d9645SMika Westerberg PINCTRL_PIN(70, "GSPI1_CLK_LOOPBK"), 458653d9645SMika Westerberg /* vGPIO_0 */ 459653d9645SMika Westerberg PINCTRL_PIN(71, "ESPI_USB_OCB_0"), 460653d9645SMika Westerberg PINCTRL_PIN(72, "ESPI_USB_OCB_1"), 461653d9645SMika Westerberg PINCTRL_PIN(73, "ESPI_USB_OCB_2"), 462653d9645SMika Westerberg PINCTRL_PIN(74, "ESPI_USB_OCB_3"), 463653d9645SMika Westerberg PINCTRL_PIN(75, "USB_CPU_OCB_0"), 464653d9645SMika Westerberg PINCTRL_PIN(76, "USB_CPU_OCB_1"), 465653d9645SMika Westerberg PINCTRL_PIN(77, "USB_CPU_OCB_2"), 466653d9645SMika Westerberg PINCTRL_PIN(78, "USB_CPU_OCB_3"), 467653d9645SMika Westerberg /* GPP_D */ 468653d9645SMika Westerberg PINCTRL_PIN(79, "SPI1_CSB"), 469653d9645SMika Westerberg PINCTRL_PIN(80, "SPI1_CLK"), 470653d9645SMika Westerberg PINCTRL_PIN(81, "SPI1_MISO_IO_1"), 471653d9645SMika Westerberg PINCTRL_PIN(82, "SPI1_MOSI_IO_0"), 472653d9645SMika Westerberg PINCTRL_PIN(83, "SML1CLK"), 473653d9645SMika Westerberg PINCTRL_PIN(84, "I2S2_SFRM"), 474653d9645SMika Westerberg PINCTRL_PIN(85, "I2S2_TXD"), 475653d9645SMika Westerberg PINCTRL_PIN(86, "I2S2_RXD"), 476653d9645SMika Westerberg PINCTRL_PIN(87, "I2S2_SCLK"), 477653d9645SMika Westerberg PINCTRL_PIN(88, "SML0CLK"), 478653d9645SMika Westerberg PINCTRL_PIN(89, "SML0DATA"), 479653d9645SMika Westerberg PINCTRL_PIN(90, "GPP_D_11"), 480653d9645SMika Westerberg PINCTRL_PIN(91, "ISH_UART0_CTSB"), 481653d9645SMika Westerberg PINCTRL_PIN(92, "SPI1_IO_2"), 482653d9645SMika Westerberg PINCTRL_PIN(93, "SPI1_IO_3"), 483653d9645SMika Westerberg PINCTRL_PIN(94, "SML1DATA"), 484653d9645SMika Westerberg PINCTRL_PIN(95, "GSPI3_CS0B"), 485653d9645SMika Westerberg PINCTRL_PIN(96, "GSPI3_CLK"), 486653d9645SMika Westerberg PINCTRL_PIN(97, "GSPI3_MISO"), 487653d9645SMika Westerberg PINCTRL_PIN(98, "GSPI3_MOSI"), 488653d9645SMika Westerberg PINCTRL_PIN(99, "UART3_RXD"), 489653d9645SMika Westerberg PINCTRL_PIN(100, "UART3_TXD"), 490653d9645SMika Westerberg PINCTRL_PIN(101, "UART3_RTSB"), 491653d9645SMika Westerberg PINCTRL_PIN(102, "UART3_CTSB"), 492653d9645SMika Westerberg PINCTRL_PIN(103, "SPI1_CLK_LOOPBK"), 493653d9645SMika Westerberg PINCTRL_PIN(104, "GSPI3_CLK_LOOPBK"), 494653d9645SMika Westerberg /* GPP_C */ 495653d9645SMika Westerberg PINCTRL_PIN(105, "SMBCLK"), 496653d9645SMika Westerberg PINCTRL_PIN(106, "SMBDATA"), 497653d9645SMika Westerberg PINCTRL_PIN(107, "SMBALERTB"), 498653d9645SMika Westerberg PINCTRL_PIN(108, "ISH_UART0_RXD"), 499653d9645SMika Westerberg PINCTRL_PIN(109, "ISH_UART0_TXD"), 500653d9645SMika Westerberg PINCTRL_PIN(110, "SML0ALERTB"), 501653d9645SMika Westerberg PINCTRL_PIN(111, "ISH_I2C2_SDA"), 502653d9645SMika Westerberg PINCTRL_PIN(112, "ISH_I2C2_SCL"), 503653d9645SMika Westerberg PINCTRL_PIN(113, "UART0_RXD"), 504653d9645SMika Westerberg PINCTRL_PIN(114, "UART0_TXD"), 505653d9645SMika Westerberg PINCTRL_PIN(115, "UART0_RTSB"), 506653d9645SMika Westerberg PINCTRL_PIN(116, "UART0_CTSB"), 507653d9645SMika Westerberg PINCTRL_PIN(117, "UART1_RXD"), 508653d9645SMika Westerberg PINCTRL_PIN(118, "UART1_TXD"), 509653d9645SMika Westerberg PINCTRL_PIN(119, "UART1_RTSB"), 510653d9645SMika Westerberg PINCTRL_PIN(120, "UART1_CTSB"), 511653d9645SMika Westerberg PINCTRL_PIN(121, "I2C0_SDA"), 512653d9645SMika Westerberg PINCTRL_PIN(122, "I2C0_SCL"), 513653d9645SMika Westerberg PINCTRL_PIN(123, "I2C1_SDA"), 514653d9645SMika Westerberg PINCTRL_PIN(124, "I2C1_SCL"), 515653d9645SMika Westerberg PINCTRL_PIN(125, "UART2_RXD"), 516653d9645SMika Westerberg PINCTRL_PIN(126, "UART2_TXD"), 517653d9645SMika Westerberg PINCTRL_PIN(127, "UART2_RTSB"), 518653d9645SMika Westerberg PINCTRL_PIN(128, "UART2_CTSB"), 519653d9645SMika Westerberg /* GPP_S */ 520653d9645SMika Westerberg PINCTRL_PIN(129, "SNDW1_CLK"), 521653d9645SMika Westerberg PINCTRL_PIN(130, "SNDW1_DATA"), 522653d9645SMika Westerberg PINCTRL_PIN(131, "SNDW2_CLK"), 523653d9645SMika Westerberg PINCTRL_PIN(132, "SNDW2_DATA"), 524653d9645SMika Westerberg PINCTRL_PIN(133, "SNDW3_CLK"), 525653d9645SMika Westerberg PINCTRL_PIN(134, "SNDW3_DATA"), 526653d9645SMika Westerberg PINCTRL_PIN(135, "SNDW4_CLK"), 527653d9645SMika Westerberg PINCTRL_PIN(136, "SNDW4_DATA"), 528653d9645SMika Westerberg /* GPP_G */ 529653d9645SMika Westerberg PINCTRL_PIN(137, "DDPA_CTRLCLK"), 530653d9645SMika Westerberg PINCTRL_PIN(138, "DDPA_CTRLDATA"), 531653d9645SMika Westerberg PINCTRL_PIN(139, "DNX_FORCE_RELOAD"), 532653d9645SMika Westerberg PINCTRL_PIN(140, "GMII_MDC_0"), 533653d9645SMika Westerberg PINCTRL_PIN(141, "GMII_MDIO_0"), 534653d9645SMika Westerberg PINCTRL_PIN(142, "SLP_DRAMB"), 535653d9645SMika Westerberg PINCTRL_PIN(143, "GPPC_G_6"), 536653d9645SMika Westerberg PINCTRL_PIN(144, "GPPC_G_7"), 537653d9645SMika Westerberg PINCTRL_PIN(145, "ISH_SPI_CSB"), 538653d9645SMika Westerberg PINCTRL_PIN(146, "ISH_SPI_CLK"), 539653d9645SMika Westerberg PINCTRL_PIN(147, "ISH_SPI_MISO"), 540653d9645SMika Westerberg PINCTRL_PIN(148, "ISH_SPI_MOSI"), 541653d9645SMika Westerberg PINCTRL_PIN(149, "DDP1_CTRLCLK"), 542653d9645SMika Westerberg PINCTRL_PIN(150, "DDP1_CTRLDATA"), 543653d9645SMika Westerberg PINCTRL_PIN(151, "DDP2_CTRLCLK"), 544653d9645SMika Westerberg PINCTRL_PIN(152, "DDP2_CTRLDATA"), 545653d9645SMika Westerberg PINCTRL_PIN(153, "GSPI2_CLK_LOOPBK"), 546653d9645SMika Westerberg /* vGPIO */ 547653d9645SMika Westerberg PINCTRL_PIN(154, "CNV_BTEN"), 548653d9645SMika Westerberg PINCTRL_PIN(155, "CNV_BT_HOST_WAKEB"), 549653d9645SMika Westerberg PINCTRL_PIN(156, "CNV_BT_IF_SELECT"), 550653d9645SMika Westerberg PINCTRL_PIN(157, "vCNV_BT_UART_TXD"), 551653d9645SMika Westerberg PINCTRL_PIN(158, "vCNV_BT_UART_RXD"), 552653d9645SMika Westerberg PINCTRL_PIN(159, "vCNV_BT_UART_CTS_B"), 553653d9645SMika Westerberg PINCTRL_PIN(160, "vCNV_BT_UART_RTS_B"), 554653d9645SMika Westerberg PINCTRL_PIN(161, "vCNV_MFUART1_TXD"), 555653d9645SMika Westerberg PINCTRL_PIN(162, "vCNV_MFUART1_RXD"), 556653d9645SMika Westerberg PINCTRL_PIN(163, "vCNV_MFUART1_CTS_B"), 557653d9645SMika Westerberg PINCTRL_PIN(164, "vCNV_MFUART1_RTS_B"), 558653d9645SMika Westerberg PINCTRL_PIN(165, "vUART0_TXD"), 559653d9645SMika Westerberg PINCTRL_PIN(166, "vUART0_RXD"), 560653d9645SMika Westerberg PINCTRL_PIN(167, "vUART0_CTS_B"), 561653d9645SMika Westerberg PINCTRL_PIN(168, "vUART0_RTS_B"), 562653d9645SMika Westerberg PINCTRL_PIN(169, "vISH_UART0_TXD"), 563653d9645SMika Westerberg PINCTRL_PIN(170, "vISH_UART0_RXD"), 564653d9645SMika Westerberg PINCTRL_PIN(171, "vISH_UART0_CTS_B"), 565653d9645SMika Westerberg PINCTRL_PIN(172, "vISH_UART0_RTS_B"), 566653d9645SMika Westerberg PINCTRL_PIN(173, "vCNV_BT_I2S_BCLK"), 567653d9645SMika Westerberg PINCTRL_PIN(174, "vCNV_BT_I2S_WS_SYNC"), 568653d9645SMika Westerberg PINCTRL_PIN(175, "vCNV_BT_I2S_SDO"), 569653d9645SMika Westerberg PINCTRL_PIN(176, "vCNV_BT_I2S_SDI"), 570653d9645SMika Westerberg PINCTRL_PIN(177, "vI2S2_SCLK"), 571653d9645SMika Westerberg PINCTRL_PIN(178, "vI2S2_SFRM"), 572653d9645SMika Westerberg PINCTRL_PIN(179, "vI2S2_TXD"), 573653d9645SMika Westerberg PINCTRL_PIN(180, "vI2S2_RXD"), 574653d9645SMika Westerberg /* GPP_E */ 575653d9645SMika Westerberg PINCTRL_PIN(181, "SATAXPCIE_0"), 576653d9645SMika Westerberg PINCTRL_PIN(182, "SATAXPCIE_1"), 577653d9645SMika Westerberg PINCTRL_PIN(183, "SATAXPCIE_2"), 578653d9645SMika Westerberg PINCTRL_PIN(184, "CPU_GP_0"), 579653d9645SMika Westerberg PINCTRL_PIN(185, "SATA_DEVSLP_0"), 580653d9645SMika Westerberg PINCTRL_PIN(186, "SATA_DEVSLP_1"), 581653d9645SMika Westerberg PINCTRL_PIN(187, "SATA_DEVSLP_2"), 582653d9645SMika Westerberg PINCTRL_PIN(188, "CPU_GP_1"), 583653d9645SMika Westerberg PINCTRL_PIN(189, "SATA_LEDB"), 584653d9645SMika Westerberg PINCTRL_PIN(190, "USB2_OCB_0"), 585653d9645SMika Westerberg PINCTRL_PIN(191, "USB2_OCB_1"), 586653d9645SMika Westerberg PINCTRL_PIN(192, "USB2_OCB_2"), 587653d9645SMika Westerberg PINCTRL_PIN(193, "USB2_OCB_3"), 588653d9645SMika Westerberg /* GPP_F */ 589653d9645SMika Westerberg PINCTRL_PIN(194, "SATAXPCIE_3"), 590653d9645SMika Westerberg PINCTRL_PIN(195, "SATAXPCIE_4"), 591653d9645SMika Westerberg PINCTRL_PIN(196, "SATAXPCIE_5"), 592653d9645SMika Westerberg PINCTRL_PIN(197, "SATAXPCIE_6"), 593653d9645SMika Westerberg PINCTRL_PIN(198, "SATAXPCIE_7"), 594653d9645SMika Westerberg PINCTRL_PIN(199, "SATA_DEVSLP_3"), 595653d9645SMika Westerberg PINCTRL_PIN(200, "SATA_DEVSLP_4"), 596653d9645SMika Westerberg PINCTRL_PIN(201, "SATA_DEVSLP_5"), 597653d9645SMika Westerberg PINCTRL_PIN(202, "SATA_DEVSLP_6"), 598653d9645SMika Westerberg PINCTRL_PIN(203, "SATA_DEVSLP_7"), 599653d9645SMika Westerberg PINCTRL_PIN(204, "SATA_SCLOCK"), 600653d9645SMika Westerberg PINCTRL_PIN(205, "SATA_SLOAD"), 601653d9645SMika Westerberg PINCTRL_PIN(206, "SATA_SDATAOUT1"), 602653d9645SMika Westerberg PINCTRL_PIN(207, "SATA_SDATAOUT0"), 603653d9645SMika Westerberg PINCTRL_PIN(208, "PS_ONB"), 604653d9645SMika Westerberg PINCTRL_PIN(209, "M2_SKT2_CFG_0"), 605653d9645SMika Westerberg PINCTRL_PIN(210, "M2_SKT2_CFG_1"), 606653d9645SMika Westerberg PINCTRL_PIN(211, "M2_SKT2_CFG_2"), 607653d9645SMika Westerberg PINCTRL_PIN(212, "M2_SKT2_CFG_3"), 608653d9645SMika Westerberg PINCTRL_PIN(213, "L_VDDEN"), 609653d9645SMika Westerberg PINCTRL_PIN(214, "L_BKLTEN"), 610653d9645SMika Westerberg PINCTRL_PIN(215, "L_BKLTCTL"), 611653d9645SMika Westerberg PINCTRL_PIN(216, "VNN_CTRL"), 612653d9645SMika Westerberg PINCTRL_PIN(217, "GPP_F_23"), 613653d9645SMika Westerberg /* GPP_H */ 614653d9645SMika Westerberg PINCTRL_PIN(218, "SRCCLKREQB_6"), 615653d9645SMika Westerberg PINCTRL_PIN(219, "SRCCLKREQB_7"), 616653d9645SMika Westerberg PINCTRL_PIN(220, "SRCCLKREQB_8"), 617653d9645SMika Westerberg PINCTRL_PIN(221, "SRCCLKREQB_9"), 618653d9645SMika Westerberg PINCTRL_PIN(222, "SRCCLKREQB_10"), 619653d9645SMika Westerberg PINCTRL_PIN(223, "SRCCLKREQB_11"), 620653d9645SMika Westerberg PINCTRL_PIN(224, "SRCCLKREQB_12"), 621653d9645SMika Westerberg PINCTRL_PIN(225, "SRCCLKREQB_13"), 622653d9645SMika Westerberg PINCTRL_PIN(226, "SRCCLKREQB_14"), 623653d9645SMika Westerberg PINCTRL_PIN(227, "SRCCLKREQB_15"), 624653d9645SMika Westerberg PINCTRL_PIN(228, "SML2CLK"), 625653d9645SMika Westerberg PINCTRL_PIN(229, "SML2DATA"), 626653d9645SMika Westerberg PINCTRL_PIN(230, "SML2ALERTB"), 627653d9645SMika Westerberg PINCTRL_PIN(231, "SML3CLK"), 628653d9645SMika Westerberg PINCTRL_PIN(232, "SML3DATA"), 629653d9645SMika Westerberg PINCTRL_PIN(233, "SML3ALERTB"), 630653d9645SMika Westerberg PINCTRL_PIN(234, "SML4CLK"), 631653d9645SMika Westerberg PINCTRL_PIN(235, "SML4DATA"), 632653d9645SMika Westerberg PINCTRL_PIN(236, "SML4ALERTB"), 633653d9645SMika Westerberg PINCTRL_PIN(237, "ISH_I2C0_SDA"), 634653d9645SMika Westerberg PINCTRL_PIN(238, "ISH_I2C0_SCL"), 635653d9645SMika Westerberg PINCTRL_PIN(239, "ISH_I2C1_SDA"), 636653d9645SMika Westerberg PINCTRL_PIN(240, "ISH_I2C1_SCL"), 637653d9645SMika Westerberg PINCTRL_PIN(241, "TIME_SYNC_0"), 638653d9645SMika Westerberg /* GPP_J */ 639653d9645SMika Westerberg PINCTRL_PIN(242, "CNV_PA_BLANKING"), 640653d9645SMika Westerberg PINCTRL_PIN(243, "CPU_C10_GATEB"), 641653d9645SMika Westerberg PINCTRL_PIN(244, "CNV_BRI_DT"), 642653d9645SMika Westerberg PINCTRL_PIN(245, "CNV_BRI_RSP"), 643653d9645SMika Westerberg PINCTRL_PIN(246, "CNV_RGI_DT"), 644653d9645SMika Westerberg PINCTRL_PIN(247, "CNV_RGI_RSP"), 645653d9645SMika Westerberg PINCTRL_PIN(248, "CNV_MFUART2_RXD"), 646653d9645SMika Westerberg PINCTRL_PIN(249, "CNV_MFUART2_TXD"), 647653d9645SMika Westerberg PINCTRL_PIN(250, "GPP_J_8"), 648653d9645SMika Westerberg PINCTRL_PIN(251, "GPP_J_9"), 649653d9645SMika Westerberg /* GPP_K */ 650653d9645SMika Westerberg PINCTRL_PIN(252, "GSXDOUT"), 651653d9645SMika Westerberg PINCTRL_PIN(253, "GSXSLOAD"), 652653d9645SMika Westerberg PINCTRL_PIN(254, "GSXDIN"), 653653d9645SMika Westerberg PINCTRL_PIN(255, "GSXSRESETB"), 654653d9645SMika Westerberg PINCTRL_PIN(256, "GSXCLK"), 655653d9645SMika Westerberg PINCTRL_PIN(257, "ADR_COMPLETE"), 656653d9645SMika Westerberg PINCTRL_PIN(258, "DDSP_HPD_A"), 657653d9645SMika Westerberg PINCTRL_PIN(259, "DDSP_HPD_B"), 658653d9645SMika Westerberg PINCTRL_PIN(260, "CORE_VID_0"), 659653d9645SMika Westerberg PINCTRL_PIN(261, "CORE_VID_1"), 660653d9645SMika Westerberg PINCTRL_PIN(262, "DDSP_HPD_C"), 661653d9645SMika Westerberg PINCTRL_PIN(263, "GPP_K_11"), 662653d9645SMika Westerberg PINCTRL_PIN(264, "SYS_PWROK"), 663653d9645SMika Westerberg PINCTRL_PIN(265, "SYS_RESETB"), 664653d9645SMika Westerberg PINCTRL_PIN(266, "MLK_RSTB"), 665653d9645SMika Westerberg /* GPP_I */ 666653d9645SMika Westerberg PINCTRL_PIN(267, "PMCALERTB"), 667653d9645SMika Westerberg PINCTRL_PIN(268, "DDSP_HPD_1"), 668653d9645SMika Westerberg PINCTRL_PIN(269, "DDSP_HPD_2"), 669653d9645SMika Westerberg PINCTRL_PIN(270, "DDSP_HPD_3"), 670653d9645SMika Westerberg PINCTRL_PIN(271, "DDSP_HPD_4"), 671653d9645SMika Westerberg PINCTRL_PIN(272, "DDPB_CTRLCLK"), 672653d9645SMika Westerberg PINCTRL_PIN(273, "DDPB_CTRLDATA"), 673653d9645SMika Westerberg PINCTRL_PIN(274, "DDPC_CTRLCLK"), 674653d9645SMika Westerberg PINCTRL_PIN(275, "DDPC_CTRLDATA"), 675653d9645SMika Westerberg PINCTRL_PIN(276, "FUSA_DIAGTEST_EN"), 676653d9645SMika Westerberg PINCTRL_PIN(277, "FUSA_DIAGTEST_MODE"), 677653d9645SMika Westerberg PINCTRL_PIN(278, "USB2_OCB_4"), 678653d9645SMika Westerberg PINCTRL_PIN(279, "USB2_OCB_5"), 679653d9645SMika Westerberg PINCTRL_PIN(280, "USB2_OCB_6"), 680653d9645SMika Westerberg PINCTRL_PIN(281, "USB2_OCB_7"), 681653d9645SMika Westerberg /* JTAG */ 682653d9645SMika Westerberg PINCTRL_PIN(282, "JTAG_TDO"), 683653d9645SMika Westerberg PINCTRL_PIN(283, "JTAGX"), 684653d9645SMika Westerberg PINCTRL_PIN(284, "PRDYB"), 685653d9645SMika Westerberg PINCTRL_PIN(285, "PREQB"), 686653d9645SMika Westerberg PINCTRL_PIN(286, "JTAG_TDI"), 687653d9645SMika Westerberg PINCTRL_PIN(287, "JTAG_TMS"), 688653d9645SMika Westerberg PINCTRL_PIN(288, "JTAG_TCK"), 689653d9645SMika Westerberg PINCTRL_PIN(289, "DBG_PMODE"), 690653d9645SMika Westerberg PINCTRL_PIN(290, "CPU_TRSTB"), 691653d9645SMika Westerberg }; 692653d9645SMika Westerberg 693653d9645SMika Westerberg static const struct intel_padgroup tglh_community0_gpps[] = { 694653d9645SMika Westerberg TGL_GPP(0, 0, 24, 0), /* GPP_A */ 6952f658f7aSAndy Shevchenko TGL_GPP(1, 25, 44, 32), /* GPP_R */ 6962f658f7aSAndy Shevchenko TGL_GPP(2, 45, 70, 64), /* GPP_B */ 6972f658f7aSAndy Shevchenko TGL_GPP(3, 71, 78, 96), /* vGPIO_0 */ 698653d9645SMika Westerberg }; 699653d9645SMika Westerberg 700653d9645SMika Westerberg static const struct intel_padgroup tglh_community1_gpps[] = { 7012f658f7aSAndy Shevchenko TGL_GPP(0, 79, 104, 128), /* GPP_D */ 7022f658f7aSAndy Shevchenko TGL_GPP(1, 105, 128, 160), /* GPP_C */ 7032f658f7aSAndy Shevchenko TGL_GPP(2, 129, 136, 192), /* GPP_S */ 7042f658f7aSAndy Shevchenko TGL_GPP(3, 137, 153, 224), /* GPP_G */ 7052f658f7aSAndy Shevchenko TGL_GPP(4, 154, 180, 256), /* vGPIO */ 706653d9645SMika Westerberg }; 707653d9645SMika Westerberg 708653d9645SMika Westerberg static const struct intel_padgroup tglh_community3_gpps[] = { 7092f658f7aSAndy Shevchenko TGL_GPP(0, 181, 193, 288), /* GPP_E */ 7102f658f7aSAndy Shevchenko TGL_GPP(1, 194, 217, 320), /* GPP_F */ 711653d9645SMika Westerberg }; 712653d9645SMika Westerberg 713653d9645SMika Westerberg static const struct intel_padgroup tglh_community4_gpps[] = { 7142f658f7aSAndy Shevchenko TGL_GPP(0, 218, 241, 352), /* GPP_H */ 715653d9645SMika Westerberg TGL_GPP(1, 242, 251, 384), /* GPP_J */ 7162f658f7aSAndy Shevchenko TGL_GPP(2, 252, 266, 416), /* GPP_K */ 717653d9645SMika Westerberg }; 718653d9645SMika Westerberg 719653d9645SMika Westerberg static const struct intel_padgroup tglh_community5_gpps[] = { 7202f658f7aSAndy Shevchenko TGL_GPP(0, 267, 281, 448), /* GPP_I */ 721653d9645SMika Westerberg TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 722653d9645SMika Westerberg }; 723653d9645SMika Westerberg 724653d9645SMika Westerberg static const struct intel_community tglh_communities[] = { 725cb8cc185SAndy Shevchenko TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps), 726cb8cc185SAndy Shevchenko TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps), 727cb8cc185SAndy Shevchenko TGL_H_COMMUNITY(2, 181, 217, tglh_community3_gpps), 728cb8cc185SAndy Shevchenko TGL_H_COMMUNITY(3, 218, 266, tglh_community4_gpps), 729cb8cc185SAndy Shevchenko TGL_H_COMMUNITY(4, 267, 290, tglh_community5_gpps), 730653d9645SMika Westerberg }; 731653d9645SMika Westerberg 732653d9645SMika Westerberg static const struct intel_pinctrl_soc_data tglh_soc_data = { 733653d9645SMika Westerberg .pins = tglh_pins, 734653d9645SMika Westerberg .npins = ARRAY_SIZE(tglh_pins), 735653d9645SMika Westerberg .communities = tglh_communities, 736653d9645SMika Westerberg .ncommunities = ARRAY_SIZE(tglh_communities), 737653d9645SMika Westerberg }; 738653d9645SMika Westerberg 739c9ccf71fSAndy Shevchenko static const struct acpi_device_id tgl_pinctrl_acpi_match[] = { 740cd0a3237SMika Westerberg { "INT34C5", (kernel_ulong_t)&tgllp_soc_data }, 741653d9645SMika Westerberg { "INT34C6", (kernel_ulong_t)&tglh_soc_data }, 7420e793a4eSAndy Shevchenko { "INTC1055", (kernel_ulong_t)&tgllp_soc_data }, 743c9ccf71fSAndy Shevchenko { } 744c9ccf71fSAndy Shevchenko }; 745c9ccf71fSAndy Shevchenko MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); 746c9ccf71fSAndy Shevchenko 747c9ccf71fSAndy Shevchenko static struct platform_driver tgl_pinctrl_driver = { 748cd0a3237SMika Westerberg .probe = intel_pinctrl_probe_by_hid, 749c9ccf71fSAndy Shevchenko .driver = { 750c9ccf71fSAndy Shevchenko .name = "tigerlake-pinctrl", 751c9ccf71fSAndy Shevchenko .acpi_match_table = tgl_pinctrl_acpi_match, 752*ee4c71f5SAndy Shevchenko .pm = pm_sleep_ptr(&intel_pinctrl_pm_ops), 753c9ccf71fSAndy Shevchenko }, 754c9ccf71fSAndy Shevchenko }; 755c9ccf71fSAndy Shevchenko module_platform_driver(tgl_pinctrl_driver); 756c9ccf71fSAndy Shevchenko 757c9ccf71fSAndy Shevchenko MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 758c9ccf71fSAndy Shevchenko MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 759c9ccf71fSAndy Shevchenko MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver"); 760c9ccf71fSAndy Shevchenko MODULE_LICENSE("GPL v2"); 76134393c36SAndy Shevchenko MODULE_IMPORT_NS(PINCTRL_INTEL); 762