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/linux/lib/crypto/powerpc/
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
78 stdu 1,-752(1)
84 SAVE_GPR 18, 144, 1
91 SAVE_GPR 25, 200, 1
105 SAVE_VRS 25, 80, 9
117 SAVE_VSX 18, 256, 9
124 SAVE_VSX 25, 368, 9
[all …]
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
[all …]
/linux/arch/alpha/include/asm/
H A Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
56 ldq $1,0($18) \n\
58 ldq $3,8($18) \n\
61 ldq $5,16($18) \n\
63 ldq $7,24($18) \n\
66 ldq $20,32($18) \n\
68 ldq $22,40($18) \n\
71 ldq $24,48($18) \n\
[all …]
H A Dpal.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 :"$1", "$16", "$22", "$23", "$24", "$25"); \
38 : "$1", "$22", "$23", "$24", "$25"); \
50 : "$1", "$22", "$23", "$24", "$25"); \
62 : "$1", "$22", "$23", "$24", "$25"); \
76 : "$1", "$22", "$23", "$24", "$25"); \
106 :"$0", "$1", "$22", "$23", "$24", "$25"); \
113 #define tbiap() __tbi(-1, /* no second argument */)
114 #define tbia() __tbi(-2, /* no second argument */)
129 : "$17", "$18", "$19", "$20", "$21"); in qemu_get_walltime()
[all …]
/linux/lib/crypto/arm64/
H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
17 * assemblers both consider the SHA-512 instructions to be part of the
20 * versions.) "sha3" doesn't make a lot of sense, since SHA-512 is part
21 * of the SHA-2 family of algorithms, and also the Arm Architecture
25 .arch armv8-a+sha3
28 * The SHA-512 round constants
102 ld1 {v8.2d-v11.2d}, [x0]
106 ld1 {v20.2d-v23.2d}, [x3], #64
109 0: ld1 {v12.2d-v15.2d}, [x1], #64
[all …]
/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
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/linux/include/dt-bindings/memory/
H A Dmt8195-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
20 * modules dma-address-region larbs-ports
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
118 #define M4U_PORT_L9_IMG_YUVO_T5_B MTK_M4U_ID(9, 18)
140 #define M4U_PORT_L10_IMG_FEO_D1_A MTK_M4U_ID(10, 18)
230 #define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0)
231 #define M4U_PORT_L18_CAM_CCUO MTK_M4U_ID(18, 1)
232 #define M4U_PORT_L18_CAM_CCUI2 MTK_M4U_ID(18, 2)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
47 #define MT_RXD2_NORMAL_LLC_MIS BIT(25)
54 #define MT_RXD2_NORMAL_CM BIT(18)
64 #define MT_RXD3_NORMAL_WOL GENMASK(18, 14)
77 #define MT_RXV1_HT_AGGR BIT(18)
108 #define MT_RXV5_LTF_PROC_TIME GENMASK(25, 19)
109 #define MT_RXV5_FOE GENMASK(18, 7)
115 #define MT_RXV6_NS_TS_FIELD GENMASK(27, 25)
[all …]
/linux/drivers/media/platform/verisilicon/
H A Drockchip_vpu981_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
64 #define av1_allow_warp AV1_DEC_REG(5, 18, 0x1)
70 #define av1_strm_start_bit AV1_DEC_REG(5, 25, 0x7f)
140 #define av1_qp_delta_ch_dc_av1 AV1_DEC_REG(13, 18, 0x7f)
141 #define av1_qp_delta_y_dc_av1 AV1_DEC_REG(13, 25, 0x7f)
171 #define av1_quant_seg4 AV1_DEC_REG(18, 0, 0xff)
172 #define av1_filt_level_seg4 AV1_DEC_REG(18, 8, 0x3f)
173 #define av1_skip_seg4 AV1_DEC_REG(18, 14, 0x1)
174 #define av1_refpic_seg4 AV1_DEC_REG(18, 15, 0xf)
175 #define av1_filt_level_delta0_seg4 AV1_DEC_REG(18, 19, 0x7f)
[all …]
H A Dhantro_g2_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
61 #define g2_start_bit G2_DEC_REG(5, 25, 0x7f)
76 #define g2_filter_over_slices G2_DEC_REG(7, 25, 0x1)
83 #define g2_filter_override G2_DEC_REG(7, 18, 0x1)
109 #define g2_init_qp_old G2_DEC_REG(10, 25, 0x3f)
147 #define hevc_rlist_b2 G2_DEC_REG(14, 25, 0x1f)
154 #define hevc_rlist_b5 G2_DEC_REG(15, 25, 0x1f)
161 #define hevc_rlist_b8 G2_DEC_REG(16, 25, 0x1f)
168 #define hevc_rlist_b11 G2_DEC_REG(17, 25, 0x1f)
170 #define hevc_rlist_f12 G2_DEC_REG(18, 0, 0x1f)
[all …]
/linux/security/apparmor/include/
H A Dsig_names.h14 [SIGTRAP] = 5, /* -, 5, - */
15 [SIGABRT] = 6, /* SIGIOT: -, 6, - */
26 [SIGSTKFLT] = 16, /* -, 16, - */
28 [SIGCHLD] = 17, /* 20, 17, 18. SIGCHLD -, -, 18 */
29 [SIGCONT] = 18, /* 19, 18, 25 */
31 [SIGTSTP] = 20, /* 18, 20, 24 */
36 [SIGXFSZ] = 25, /* 25, 25, 31 */
41 [SIGPWR] = 30, /* 29, 30, 19. SIGINFO 29, -, - */
46 [SIGEMT] = 32, /* 7, - , 7 */
53 [SIGUNUSED] = 34, /* -, 31, - */
/linux/drivers/comedi/drivers/ni_routing/ni_device_routes/
H A Dpci-6602.c1 // SPDX-License-Identifier: GPL-2.0+
3 * comedi/drivers/ni_routing/ni_device_routes/pci-6602.c
6 * COMEDI - Linux Control and Measurement Device Interface
31 .device = "pci-6602",
275 .dest = NI_PFI(18),
395 .dest = NI_PFI(25),
446 NI_PFI(18),
478 NI_PFI(18),
525 NI_PFI(25),
557 NI_PFI(25),
[all …]
/linux/include/dt-bindings/clock/
H A Dexynos5433.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define CLK_MOUT_ACLK_CAM1_552_B 18
29 #define CLK_MOUT_ACLK_GSCL_333 25
219 #define CLK_MOUT_CLK2X_PHY_C 18
226 #define CLK_MOUT_ACLK_MIFNM_400 25
413 #define CLK_PCLK_I2C0 18
420 #define CLK_PCLK_HSI2C7 25
483 #define CLK_PCLK_TZPC8 18
490 #define CLK_PCLK_TZPC1 25
526 #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18
[all …]
H A Dmediatek,mt8196-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
31 #define CLK_TOP_MCINFRA 18
38 #define CLK_TOP_SPI2_BCLK 25
173 #define CLK_TOP2_MDP 18
180 #define CLK_TOP2_MAINPLL2_D4 25
277 #define CLK_PERI_AO_SPI6_BCLK 18
284 #define CLK_PERI_AO_MSDC2_MSDC_SRC 25
351 #define CLK_VLP_CAMTG0 18
358 #define CLK_VLP_CAMTG7 25
402 #define CLK_MM_DISP_DLI_ASYNC0 18
[all …]
H A Dexynos5260-clk.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define TOP_MOUT_SCLK_PERI_UART0_UCLK 18
40 #define TOP_MOUT_BUS2_BUSTOP_400 25
187 #define MIF_DOUT_MEDIA_PLL 18
194 #define MIF_CLK_INTMEM 25
252 #define GSCL_CLK_SMMU3_LITE_D 18
259 #define GSCL_SCLK_CSIS1_WRAP 25
281 #define FSYS_PHYCLK_USBHOST20 18
302 #define PERI_CLK_I2C5 18
309 #define PERI_CLK_EFUSE_WRITER 25
[all …]
H A Dspacemit,k1-syscon.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
3 * Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com>
28 #define CLK_PLL2_D3 18
35 #define CLK_PLL3_D2 25
65 #define CLK_PLL1_245P76 18
72 #define CLK_SLOW_UART1 25
107 #define CLK_PWM8 18
114 #define CLK_PWM15 25
211 #define RESET_PWM8 18
218 #define RESET_PWM15 25
[all …]
H A Dsprd,ums512-clk.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
29 #define CLK_MPLL0_GATE 18
68 #define CLK_TWPLL_38M4 18
75 #define CLK_LPLL_30M72 25
103 #define CLK_AP_CE 18
110 #define CLK_DSI_APB 25
146 #define CLK_AON_IIS 18
153 #define CLK_DJTAG_TCK 25
209 #define CLK_MBOX_EB 18
216 #define CLK_SPLK_EB 25
[all …]
H A Dsprd,sc9860-clk.h1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
28 #define CLK_RPLL0_GATE 18
52 #define CLK_TWPLL_12M 18
59 #define CLK_TWPLL_76M8 25
101 #define CLK_IIS1 18
124 #define CLK_PWM0 18
131 #define CLK_THM 25
182 #define CLK_AP_INTC1_EB 18
189 #define CLK_PIN_EB 25
327 #define CLK_ISP_PCLK_EB 18
[all …]
H A Dimx8ulp-clock.h1 /* SPDX-License-Identifier: GPL-2.0+ OR MIT */
25 #define IMX8ULP_CLK_SPLL3_PFD1_DIV2 18
32 #define IMX8ULP_CLK_NIC_PER_DIVPLAT 25
85 #define IMX8ULP_CLK_PLL4_PFD2_DIV2_GATE 18
92 #define IMX8ULP_CLK_PLL4_PFD2_DIV1 25
138 #define IMX8ULP_CLK_DMA1_CH4 18
145 #define IMX8ULP_CLK_DMA1_CH11 25
190 #define IMX8ULP_CLK_USB_XBAR 18
217 #define IMX8ULP_CLK_RGPIOD 18
224 #define IMX8ULP_CLK_DMA2_CH5 25
/linux/include/linux/netfilter/
H A Dnf_conntrack_h323_types.h1 /* SPDX-License-Identifier: GPL-2.0-only */
147 eH2250LogicalChannelParameters_silenceSuppression = (1 << 25),
259 eSetup_UUIE_callServices = (1 << 25),
266 eSetup_UUIE_fastStart = (1 << 18),
305 eCallProceeding_UUIE_multipleCalls = (1 << 25),
327 eConnect_UUIE_multipleCalls = (1 << 25),
334 eConnect_UUIE_serviceControl = (1 << 18),
355 eAlerting_UUIE_multipleCalls = (1 << 25),
362 eAlerting_UUIE_capacity = (1 << 18),
398 eFacility_UUIE_tokens = (1 << 25),
[all …]
/linux/arch/riscv/include/asm/
H A Dgpr-num.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
29 .equ .L__gpr_num_s2, 18
36 .equ .L__gpr_num_s9, 25
47 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31\n"…
68 " .equ .L__gpr_num_s2, 18\n" \
75 " .equ .L__gpr_num_s9, 25\n" \
/linux/arch/alpha/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Kernel entry-points.
8 #include <asm/asm-offsets.h>
30 .cfi_rel_offset $18, 40
35 .size \func, . - \func
39 * This defines the normal kernel pt-regs layout.
41 * regs 9-15 preserved by C code
42 * regs 16-18 saved by PAL-code
43 * regs 29-30 saved and set up by PAL-code
44 * JRP - Save regs 16-18 in a special area of the stack, so that
[all …]
/linux/arch/mips/include/asm/
H A Dmipsregs.h19 #include <asm/isa-rev.h>
184 #define CP0_WATCHLO $18
185 #define C0_WATCHLO 18, 0
208 #define CP0_PERFORMANCE $25
209 #define C0_PERFORMANCE 25, 0
249 #define CP0_IWATCH $18
290 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
291 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
372 #define PL_256K 18
522 /* in-kernel enabled CUs */
[all …]
H A Dregdef.h8 * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
10 * written by Ralf Baechle <ralf@linux-mips.org>
44 #define GPR_S2 18
51 #define GPR_T9 25
52 #define GPR_JP 25 /* PIC jump register */
67 #define GPR_V0 2 /* return value - caller saved */
87 #define GPR_S2 18
94 #define GPR_T9 25 /* callee address for PIC/temp */
95 #define GPR_JP 25 /* PIC jump register */
98 #define GPR_GP 28 /* global pointer - caller saved for PIC */
[all …]
/linux/drivers/video/fbdev/
H A Dau1200fb.h64 uint32 reserved2[(0x0100-0x0058)/4];
77 uint32 reserved3[(0x0400-0x0180)/4];
79 volatile uint32 palette[(0x0800-0x0400)/4];
92 #define LCD_SCREEN_SX_N(WIDTH) ((WIDTH-1)<<19)
93 #define LCD_SCREEN_SY_N(HEIGHT) ((HEIGHT-1)<<8)
141 #define LCD_WINCTRL1_FRM (0xF<<25)
146 #define LCD_WINCTRL1_FRM_1BPP (0<<25)
147 #define LCD_WINCTRL1_FRM_2BPP (1<<25)
148 #define LCD_WINCTRL1_FRM_4BPP (2<<25)
149 #define LCD_WINCTRL1_FRM_8BPP (3<<25)
[all …]

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