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/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
10 "Unit": "CPU-M-CF",
14 …s been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Leve…
17 "Unit": "CPU-M-CF",
21 …rogress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in pr…
24 "Unit": "CPU-M-CF",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
31 "Unit": "CPU-M-CF",
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z17/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
10 "Unit": "CPU-M-CF",
14 …s been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Leve…
17 "Unit": "CPU-M-CF",
21 …rogress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in pr…
24 "Unit": "CPU-M-CF",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
31 "Unit": "CPU-M-CF",
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A Dcache.json111 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
114 …iption": "Level 1 data cache refill started due to prefetch. Counts any linefills from the prefetc…
117 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
120 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
123 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
126 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
141 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
144 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
147 …"PublicDescription": "Level 3 cache write streaming mode. This event counts for each cycle where t…
150 …"BriefDescription": "Level 3 cache write streaming mode. This event counts for each cycle where th…
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dcache.json105 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
108 …Level 3 cache refill due to prefetch. This event counts any linefills from the hardware prefetcher…
111 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
114 …Level 2 cache refill due to prefetch. +//0 If the core is configured with a per-core L2 cache: Thi…
117 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
120 …ption": "Level 1 data cache refill due to prefetch. This event counts any linefills from the prefe…
123 …"PublicDescription": "Level 2 cache write streaming mode. This event counts for each cycle where t…
126 …"BriefDescription": "Level 2 cache write streaming mode. This event counts for each cycle where th…
129 …"PublicDescription": "Level 1 data cache entering write streaming mode.This event counts for each …
132 …"BriefDescription": "Level 1 data cache entering write streaming mode.This event counts for each e…
[all …]
/linux/drivers/gpu/drm/amd/include/ivsrcid/dcn/
H A Dirqsrcs_dcn_1_0.h30 …C_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level
33 … // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
36 … // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
37 #define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2
39 … // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
42 … // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
45 … // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
48 … // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
51 …DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level
54 …DC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse
[all …]
/linux/tools/power/x86/intel-speed-select/
H A Disst-display.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel dynamic_speed_select -- Enumerate and control features
26 str_len - curr_index, ","); in printcpulist()
31 index = snprintf(&str[curr_index], str_len - curr_index, "%d", in printcpulist()
67 for (i = size - 1; i >= 0; --i) { in printcpumask()
68 index = snprintf(&str[curr_index], str_len - curr_index, "%08x", in printcpumask()
74 strncat(&str[curr_index], ",", str_len - curr_index); in printcpumask()
84 static void format_and_print_txt(FILE *outf, int level, char *header, in format_and_print_txt() argument
91 if (!level) in format_and_print_txt()
94 if (level == 1) { in format_and_print_txt()
[all …]
/linux/lib/zstd/compress/
H A Dclevels.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
18 /*-===== Pre-defined compression levels =====-*/
25 { /* "default" - for any srcSize > 256 KB */
28 { 19, 13, 14, 1, 7, 0, ZSTD_fast }, /* level 1 */
29 { 20, 15, 16, 1, 6, 0, ZSTD_fast }, /* level 2 */
30 { 21, 16, 17, 1, 5, 0, ZSTD_dfast }, /* level 3 */
31 { 21, 18, 18, 1, 5, 0, ZSTD_dfast }, /* level 4 */
32 { 21, 18, 19, 3, 5, 2, ZSTD_greedy }, /* level 5 */
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/
H A Dl2_cache.json4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access…
8 …refills into the level 2 cache. level 2 cache is a unified cache for data and instruction accesses…
12 …"PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includ…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a…
28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access…
32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access…
36 …"PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated in…
40 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.…
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
[all …]
H A Dmetrics.json14 …"MetricExpr": "(100 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (STALL_SLOT / (CPU_CYCLES * 8)))) + ((…
60 …"MetricExpr": "(100 * ((STALL_SLOT_FRONTEND / (CPU_CYCLES * 8)) - ((BR_MIS_PRED * 4) / CPU_CYCLES)…
100 … of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gi…
107 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho…
114 …io of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This give…
121 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
128 …level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesse…
135 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed …
142 …level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. T…
149 …"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed pe…
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dl2_cache.json4 …level 2 cache accesses. level 2 cache is a unified cache for data and instruction accesses. Access…
8 …refills into the level 2 cache. level 2 cache is a unified cache for data and instruction accesses…
12 …"PublicDescription": "Counts write-backs of data from the L2 cache to outside the CPU. This includ…
20 …level 2 cache accesses due to memory read operations. level 2 cache is a unified cache for data an…
24 …level 2 cache accesses due to memory write operations. level 2 cache is a unified cache for data a…
28 …ounted by L2D_CACHE_RD. level 2 cache is a unified cache for data and instruction accesses, access…
32 …ounted by L2D_CACHE_WR. level 2 cache is a unified cache for data and instruction accesses, access…
36 …"PublicDescription": "Counts evictions from the level 2 cache because of a line being allocated in…
40 …"PublicDescription": "Counts write-backs from the level 2 cache that are a result of either:\n\n1.…
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A Dcache.json14 "BriefDescription": "L1D cache invalidate. Impacted by errata -"
107 "PublicDescription": "Level 1 data or unified cache demand access",
110 "BriefDescription": "Level 1 data or unified cache demand access"
113 "PublicDescription": "Level 1 data or unified cache preload or prefetch",
116 "BriefDescription": "Level 1 data or unified cache preload or prefetch"
119 "PublicDescription": "Level 1 data or unified cache refill, preload or prefetch",
122 "BriefDescription": "Level 1 data or unified cache refill, preload or prefetch"
149 "PublicDescription": "Level 1 prefetcher, load prefetch requests generated",
152 "BriefDescription": "Level 1 prefetcher, load prefetch requests generated"
155 "PublicDescription": "Level
8 { global() object
[all...]
/linux/tools/perf/pmu-events/arch/arm64/
H A Dcommon-and-microarch.json9 "PublicDescription": "Level 1 instruction cache refill",
12 "BriefDescription": "Level 1 instruction cache refill"
15 "PublicDescription": "Attributable Level 1 instruction TLB refill",
18 "BriefDescription": "Attributable Level 1 instruction TLB refill"
21 "PublicDescription": "Level 1 data cache refill",
24 "BriefDescription": "Level 1 data cache refill"
27 "PublicDescription": "Level 1 data cache access",
30 "BriefDescription": "Level 1 data cache access"
33 "PublicDescription": "Attributable Level 1 data TLB refill",
36 "BriefDescription": "Attributable Level 1 data TLB refill"
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2…
17 "Unit": "CPU-M-CF",
21 …e data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on thi…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A Dextended.json3 "Unit": "CPU-M-CF",
6 "BriefDescription": "L1D Read-only Exclusive Writes",
7 …"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2…
17 "Unit": "CPU-M-CF",
21 …e data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on thi…
24 "Unit": "CPU-M-CF",
27 "BriefDescription": "DTLB2 One-Megabyte Page Writes",
28 …en into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte pa…
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A Dextended.json3 "Unit": "CPU-M-CF",
7 …tion": "A directory write to the Level-1 Data Cache directory where the returned cache line was so…
10 "Unit": "CPU-M-CF",
14 …": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was…
17 "Unit": "CPU-M-CF",
21 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
24 "Unit": "CPU-M-CF",
28 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
31 "Unit": "CPU-M-CF",
35 "PublicDescription": "Incremented by one for every store sent to Level-2 cache."
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_z10/
H A Dextended.json3 "Unit": "CPU-M-CF",
7 …": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was…
10 "Unit": "CPU-M-CF",
14 …ion": "A directory write to the Level-1 Data Cache directory where the installed cache line was so…
17 "Unit": "CPU-M-CF",
21 …": "A directory write to the Level-1 Instruction Cache directory where the installed cache line wa…
24 "Unit": "CPU-M-CF",
28 …tion": "A directory write to the Level-1 Data Cache directory where the installed cache line was s…
31 "Unit": "CPU-M-CF",
35 …n": "A directory write to the Level-1 Instruction Cache directory where the installed cache line w…
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drockchip-pinconf.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /omit-if-no-ref/
8 pcfg_pull_up: pcfg-pull-up {
9 bias-pull-up;
12 /omit-if-no-ref/
13 pcfg_pull_down: pcfg-pull-down {
14 bias-pull-down;
17 /omit-if-no-ref/
18 pcfg_pull_none: pcfg-pull-none {
19 bias-disable;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
[all …]
/linux/security/selinux/ss/
H A Dconstraint.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * beyond the type-based rules in `te' or the role-based
26 #define CEXPR_AND 2 /* expr and expr */
33 #define CEXPR_ROLE 2 /* role */
37 #define CEXPR_L1L2 32 /* low level 1 vs. low level 2 */
38 #define CEXPR_L1H2 64 /* low level 1 vs. high level 2 */
39 #define CEXPR_H1L2 128 /* high level 1 vs. low level 2 */
40 #define CEXPR_H1H2 256 /* high level 1 vs. high level 2 */
41 #define CEXPR_L1H1 512 /* low level 1 vs. high level 1 */
42 #define CEXPR_L2H2 1024 /* low level 2 vs. high level 2 */
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/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-qcom-level.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-qcom-level.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niklas Cassel <nks@flawful.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2-qcom-level
20 '^opp-?[0-9]+$':
25 opp-level: true
27 qcom,opp-fuse-level:
[all …]
/linux/arch/arm64/boot/dts/amd/
H A Delba-16core.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Copyright 2020-2023 Advanced Micro Devices, Inc.
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu-map {
44 compatible = "arm,cortex-a72";
46 next-level-cache = <&l2_0>;
47 enable-method = "psci";
52 compatible = "arm,cortex-a72";
54 next-level-cache = <&l2_0>;
[all …]
/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A Dextended.json3 "Unit": "CPU-M-CF",
7 …"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB…
10 "Unit": "CPU-M-CF",
14 …"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle…
17 "Unit": "CPU-M-CF",
21 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so…
24 "Unit": "CPU-M-CF",
28 …": "A directory write to the Level-1 Instruction cache directory where the returned cache line was…
31 "Unit": "CPU-M-CF",
35 …tion": "A directory write to the Level-1 Data cache directory where the returned cache line was so…
[all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dcache.json78 …"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts …
84 …"PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event …
108 "PublicDescription": "Level 1 data cache late miss",
114 "PublicDescription": "Level 1 data cache prefetch request",
120 "PublicDescription": "Level 2 data cache prefetch request",
126 "PublicDescription": "Level 1 stage 2 TLB refill",
129 "BriefDescription": "L1 stage 2 TLB refill"
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
135 "BriefDescription": "Page walk, L0 stage-1 hit"
138 "PublicDescription": "Page walk cache level-1 stage-1 hit",
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 * Other names: H13J, "Jade Chop", "Jade", "Jade 2C"
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0>; /* To be filled by loader */
69 next-level-cache = <&l2_cache_0>;
[all …]
/linux/net/netfilter/
H A Dnf_conntrack_h323_asn1.c1 // SPDX-License-Identifier: GPL-2.0-only
40 #define OID 2
60 /* #define BITS 1-8 */
70 #define DECODE 2
100 #define INC_BIT(bs) if((++(bs)->bit)>7){(bs)->cur++;(bs)->bit=0;}
101 #define INC_BITS(bs,b) if(((bs)->bit+=(b))>7){(bs)->cur+=(bs)->bit>>3;(bs)->bit&=7;}
102 #define BYTE_ALIGN(bs) if((bs)->bit){(bs)->cur++;(bs)->bit=0;}
110 static int decode_nul(struct bitstr *bs, const struct field_t *f, char *base, int level);
111 static int decode_bool(struct bitstr *bs, const struct field_t *f, char *base, int level);
112 static int decode_oid(struct bitstr *bs, const struct field_t *f, char *base, int level);
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