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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
69 #define SPEED_PLL_MASK GENMASK(7, 2)
138 #define GEN2_TX_DATA_DLY_DEFT FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2)
156 #define MODE_MARGIN_OVERRIDE BIT(2)
161 #define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2)
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
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H A Dphy-armada38x-comphy.c1 // SPDX-License-Identifier: GPL-2.0
29 #define COMPHY_STAT1_PLL_RDY_RX BIT(2)
47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
52 * row index = serdes lane,
64 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
66 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
69 if (priv->conf) { in a38x_set_conf()
70 conf = readl_relaxed(priv->conf); in a38x_set_conf()
72 conf |= BIT(lane->port); in a38x_set_conf()
74 conf &= ~BIT(lane->port); in a38x_set_conf()
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/linux/Documentation/devicetree/bindings/usb/
H A Donnn,nb7vpq904m.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ON Semiconductor Type-C DisplayPort ALT Mode Linear Redriver
10 - Neil Armstrong <neil.armstrong@linaro.org>
15 - onnn,nb7vpq904m
20 vcc-supply:
23 enable-gpios: true
24 orientation-switch: true
25 retimer-switch: true
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/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dpio_phy_regs.h1 /* SPDX-License-Identifier: MIT */
12 #define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
13 #define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
15 #define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
19 #define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) argument
29 #define DPIO_S1_DIV_DAC 0 /* 10, DAC 25-225M rate */
30 #define DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */
31 #define DPIO_S1_DIV_LVDS1 2 /* 14 */
88 #define DPIO_PCS_CLK_DATAWIDTH_16_20 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)
115 #define DPIO_PCS_TX2DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2)
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H A Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
30 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
48 if (display->platform.pantherlake && phy < PHY_C) in intel_encoder_is_c10phy()
51 if ((display->platform.lunarlake || display->platform.meteorlake) && phy < PHY_C) in intel_encoder_is_c10phy()
74 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
75 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
77 return intel_tc_port_max_lane_count(dig_port) > 2 in intel_cx0_get_owned_lane_mask()
87 drm_WARN_ON(display->drm, !enabled); in assert_dc_off()
93 int lane; in intel_cx0_program_msgbus_timer() local
95 for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane) in intel_cx0_program_msgbus_timer()
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8qm-hsio.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <dt-bindings/phy/phy.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
46 #define HSIO_IOB_A_0_TXOE BIT(2)
96 struct imx_hsio_lane lane[MAX_NUM_LANE]; member
119 struct imx_hsio_lane *lane = phy_get_drvdata(phy); in imx_hsio_init() local
120 struct imx_hsio_priv *priv = lane->priv; in imx_hsio_init()
121 struct device *dev = priv->dev; in imx_hsio_init()
124 switch (lane->phy_type) { in imx_hsio_init()
126 lane->phy_mode = PHY_MODE_PCIE; in imx_hsio_init()
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H A Dphy-fsl-lynx-28g.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
12 #define LYNX_28G_NUM_PLL 2
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
45 /* Per SerDes lane registers */
46 /* Lane a General Control Register */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
51 #define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
55 /* Lane a Tx Reset Control Register */
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
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/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
30 * Lane Registers
33 /* TX De-emphasis parameters */
47 #define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2)
148 #define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2)
149 #define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2)
163 /* Lane 0/1/2/3 offset */
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/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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/linux/sound/soc/tegra/
H A Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION. All rights reserved.
4 // tegra186_asrc.c - Tegra186 ASRC driver
45 ASRC_STREAM_REG_DEFAULTS(2),
72 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
82 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
83 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
93 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
100 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
101 asrc->soc_data->aram_start_addr); in tegra186_asrc_runtime_resume()
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/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
86 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(x) ((x) < 2 ? 0x078 + (x) * 4 : \
92 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(x) ((x) < 2 ? 0x090 + (x) * 4 : \
96 #define XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(x) ((x) < 2 ? 0x098 + (x) * 4 : \
128 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
134 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 2
158 #define XUSB_PADCTL_HSIC_PAD_CTL1_PD_TX (1 << 2)
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
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H A Dxusb-tegra186.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
33 #define USB2_PORT_SHIFT(x) ((x) * 2)
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
80 #define USB2_OTG_PD_DR BIT(2)
140 #define UTMI_LS SPEED(2)
154 #define FAKE_USBOP_EN BIT(2)
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H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
66 USB2_PORT_WAKEUP_EVENT(2) | USB2_PORT_WAKEUP_EVENT(3) | \
68 SS_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(3) | \
75 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
106 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
146 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
188 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2)
276 (((_port) <= 2) ? (_offset1) : (_offset2))
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
73 * "force-hpd" would indicate whether driver need this. in analogix_dp_detect_hpd()
75 if (!dp->force_hpd) in analogix_dp_detect_hpd()
76 return -ETIMEDOUT; in analogix_dp_detect_hpd()
83 dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n"); in analogix_dp_detect_hpd()
88 dev_err(dp->dev, "failed to get hpd plug in status\n"); in analogix_dp_detect_hpd()
89 return -EINVAL; in analogix_dp_detect_hpd()
92 dev_dbg(dp->dev, "success to get plug in status after force hpd\n"); in analogix_dp_detect_hpd()
102 ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version); in analogix_dp_detect_sink_psr()
104 dev_err(dp->dev, "failed to get PSR version, disable it\n"); in analogix_dp_detect_sink_psr()
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/linux/drivers/net/ethernet/ti/
H A Dnetcp_xgbepcsr.c1 // SPDX-License-Identifier: GPL-2.0
7 * WingMan Kwok <w-kwok2@ti.com>
17 /* PCS-R registers */
26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s)
146 /* lane is 0 based */
148 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config() argument
152 /* lane setup */ in netcp_xgbe_serdes_lane_config()
156 (0x200 * lane), in netcp_xgbe_serdes_lane_config()
162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, in netcp_xgbe_serdes_lane_config()
166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, in netcp_xgbe_serdes_lane_config()
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/linux/drivers/media/platform/ti/omap3isp/
H A Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Bus Configuration
25 * struct isp_parallel_cfg - Parallel interface configuration
26 * @data_lane_shift: Data lane shifter
27 * 0 - CAMEXT[13:0] -> CAM[13:0]
28 * 2 - CAMEXT[13:2] -> CAM[11:0]
29 * 4 - CAMEXT[13:4] -> CAM[9:0]
30 * 6 - CAMEXT[13:6] -> CAM[7:0]
32 * 0 - Sample on rising edge, 1 - Sample on falling edge
34 * 0 - Active high, 1 - Active low
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/linux/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-usbdp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Wang <frank.wang@rock-chips.com>
11 - Zhang Yubing <yubing.zhang@rock-chips.com>
16 - rockchip,rk3576-usbdp-phy
17 - rockchip,rk3588-usbdp-phy
22 "#phy-cells":
25 - PHY_TYPE_USB3
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H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
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/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
91 struct phy *phys[2];
99 writel(value, padctl->regs + offset); in padctl_writel()
105 return readl(padctl->regs + offset); in padctl_readl()
112 return padctl->soc->num_pins; in tegra_xusb_padctl_get_groups_count()
120 return padctl->soc->pins[group].name; in tegra_xusb_padctl_get_group_name()
129 * For the tegra-xusb pad controller groups are synonymous in tegra_xusb_padctl_get_group_pins()
130 * with lanes/pins and there is always one lane/pin per group. in tegra_xusb_padctl_get_group_pins()
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/linux/drivers/phy/mediatek/
H A Dphy-mtk-pcie.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/nvmem-consumer.h>
15 #include "phy-mtk-io.h"
25 #define EFUSE_LN_TX_PMOS_SEL GENMASK(5, 2)
36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
40 * @lane_efuse_supported: software eFuse data is supported for this lane
50 * struct mtk_pcie_phy_data - phy data for each SoC
51 * @num_lanes: supported lane numbers
60 * struct mtk_pcie_phy - PCIe phy driver main structure
67 * @efuse: pointer to eFuse data for each lane
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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq5332-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
17 include/dt-bindings/clock/qcom,gcc-ipq5332.h
18 include/dt-bindings/clock/qcom,gcc-ipq5424.h
23 - qcom,ipq5332-gcc
24 - qcom,ipq5424-gcc
29 - description: Board XO clock source
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/linux/drivers/gpu/drm/hisilicon/hibmc/dp/
H A Ddp_link.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 switch (dp->link.cap.link_rate) { in hibmc_dp_get_serdes_rate_cfg()
24 return -EINVAL; in hibmc_dp_get_serdes_rate_cfg()
30 u8 buf[2]; in hibmc_dp_link_training_configure()
33 /* DP 2 lane */ in hibmc_dp_link_training_configure()
35 dp->link.cap.lanes == 0x2 ? 0x3 : 0x1); in hibmc_dp_link_training_configure()
37 dp->link.cap.lanes == 0x2 ? 0x1 : 0); in hibmc_dp_link_training_configure()
42 /* set rate and lane count */ in hibmc_dp_link_training_configure()
43 buf[0] = dp->link.cap.link_rate; in hibmc_dp_link_training_configure()
44 buf[1] = DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; in hibmc_dp_link_training_configure()
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/linux/drivers/net/ethernet/sfc/falcon/
H A Dtxc43128_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2006-2011 Solarflare Communications Inc.
9 * see www.transwitch.com, part is TXC-43128
30 * Compile-time config
52 /* Lane power-down */
56 * initiates a logic reset. Self-clearing */
63 /* Lane selection */
65 #define TXC_GSGQLCT_LNSL_WIDTH 2
69 /* Lane power-down */
77 /* Amplitude on lanes 2, 3 */
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