| /linux/Documentation/devicetree/bindings/iio/accel/ |
| H A D | lis302.txt | 8 - compatible: should be set to "st,lis3lv02d-spi"
15 - compatible: should be set to "st,lis3lv02d"
23 - st,click-single-{x,y,z}: if present, tells the device to issue an
26 - st,click-double-{x,y,z}: if present, tells the device to issue an
29 - st,click-thresh-{x,y,z}: set the x/y/z axis threshold
30 - st,click-click-time-limit: click time limit, from 0 to 127.5msec
32 - st,click-latency: click latency, from 0 to 255 msec with
33 step of 1 msec.
34 - st,click-window: click window, from 0 to 255 msec with
35 step of 1 msec.
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| /linux/Documentation/devicetree/bindings/iio/ |
| H A D | st,st-sensors.yaml | 4 $id: http://devicetree.org/schemas/iio/st,st-sensors.yaml#
16 - Denis Ciocca <denis.ciocca@st.com>
24 - st,h3lis331dl-accel
25 - st,lis2de12
26 - st,lis2dw12
27 - st,lis2hh12
28 - st,lis2dh12-accel
29 - st,lis2ds12
30 - st,lis302dl
31 - st,lis331dl-accel
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| /linux/drivers/iio/dac/ |
| H A D | ad3552r-hs.c | 72 static int ad3552r_hs_reg_read(struct ad3552r_hs_state *st, u32 reg, u32 *val, in ad3552r_hs_reg_read() argument
76 WARN_ON_ONCE(st->config_d & AD3552R_MASK_SPI_CONFIG_DDR); in ad3552r_hs_reg_read()
78 return st->data->bus_reg_read(st->back, reg, val, xfer_size); in ad3552r_hs_reg_read()
81 static int ad3552r_hs_set_data_source(struct ad3552r_hs_state *st, in ad3552r_hs_set_data_source() argument
86 for (i = 0; i < st->model_data->num_hw_channels; ++i) { in ad3552r_hs_set_data_source()
87 ret = iio_backend_data_source_set(st->back, i, type); in ad3552r_hs_set_data_source()
95 static int ad3552r_hs_update_reg_bits(struct ad3552r_hs_state *st, u32 reg, in ad3552r_hs_update_reg_bits() argument
101 ret = ad3552r_hs_reg_read(st, reg, &rval, xfer_size); in ad3552r_hs_update_reg_bits()
107 return st->data->bus_reg_write(st->back, reg, rval, xfer_size); in ad3552r_hs_update_reg_bits()
114 struct ad3552r_hs_state *st = iio_priv(indio_dev); in ad3552r_hs_read_raw() local
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| H A D | ad5592r-base.c | 26 struct ad5592r_state *st = gpiochip_get_data(chip); in ad5592r_gpio_get() local
30 scoped_guard(mutex, &st->gpio_lock) { in ad5592r_gpio_get()
31 if (st->gpio_out & BIT(offset)) in ad5592r_gpio_get()
32 val = st->gpio_val; in ad5592r_gpio_get()
34 ret = st->ops->gpio_read(st, &val); in ad5592r_gpio_get()
46 struct ad5592r_state *st = gpiochip_get_data(chip); in ad5592r_gpio_set() local
48 guard(mutex)(&st->gpio_lock); in ad5592r_gpio_set()
51 st->gpio_val |= BIT(offset); in ad5592r_gpio_set()
53 st->gpio_val &= ~BIT(offset); in ad5592r_gpio_set()
55 return st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); in ad5592r_gpio_set()
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| H A D | ad7293.c | 134 static const int dac_offset_table[] = {0, 1, 2};
136 static const int isense_gain_table[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10};
138 static const int adc_range_table[] = {0, 1, 2, 3};
150 static int ad7293_page_select(struct ad7293_state *st, unsigned int reg) in ad7293_page_select() argument
154 if (st->page_select != FIELD_GET(AD7293_PAGE_ADDR_MSK, reg)) { in ad7293_page_select()
155 st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, AD7293_REG_PAGE_SELECT); in ad7293_page_select()
156 st->data[1] = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg); in ad7293_page_select()
158 ret = spi_write(st->spi, &st->data[0], 2); in ad7293_page_select()
162 st->page_select = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg); in ad7293_page_select()
168 static int __ad7293_spi_read(struct ad7293_state *st, unsigned int reg, in __ad7293_spi_read() argument
[all …]
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| /linux/drivers/iio/adc/ |
| H A D | at91_adc.c | 34 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
35 #define AT91_ADC_START (1 << 1) /* Start Conversion */
40 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
41 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
42 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
43 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
44 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
45 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
46 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
47 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
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| H A D | ad7298.c | 32 #define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */
59 .indexed = 1, \
76 .indexed = 1,
82 .scan_index = -1,
90 AD7298_V_CHAN(1),
106 struct ad7298_state *st = iio_priv(indio_dev); in ad7298_update_scan_mode() local
115 command = AD7298_WRITE | st->ext_ref; in ad7298_update_scan_mode()
117 for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1) in ad7298_update_scan_mode()
121 st->tx_buf[0] = cpu_to_be16(command); in ad7298_update_scan_mode()
124 st->ring_xfer[0].tx_buf = &st->tx_buf[0]; in ad7298_update_scan_mode()
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| H A D | ad7606.c | 44 * X is the integer part and X + 1 is the fractional part.
83 { 0, 610352 }, { 1, 220703 }
91 1, 2, 4, 8, 16, 32, 64,
95 1, 2, 4, 8, 16, 32, 64, 128, 256,
99 1, 2, 4, 8, 16, 32, 64, 128,
103 -128, 1, 127,
194 .max_samplerate = 1 * MEGA,
246 .max_samplerate = 1 * MEGA,
262 .max_samplerate = 1 * MEGA,
276 int ad7606_reset(struct ad7606_state *st) in ad7606_reset() argument
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| H A D | ad7192.c | 38 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
61 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
62 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
80 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
91 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
110 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
134 #define AD7194_CH_POS(x) (((x) - 1) << 4)
135 #define AD7194_CH_NEG(x) ((x) - 1)
143 #define AD7194_CH_AIN_START 1
161 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
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| H A D | ad7266.c | 52 static int ad7266_wakeup(struct ad7266_state *st) in ad7266_wakeup() argument
55 return spi_read(st->spi, &st->data.sample[0], 2); in ad7266_wakeup()
58 static int ad7266_powerdown(struct ad7266_state *st) in ad7266_powerdown() argument
61 return spi_read(st->spi, &st->data.sample[0], 1); in ad7266_powerdown()
66 struct ad7266_state *st = iio_priv(indio_dev); in ad7266_preenable() local
67 return ad7266_wakeup(st); in ad7266_preenable()
72 struct ad7266_state *st = iio_priv(indio_dev); in ad7266_postdisable() local
73 return ad7266_powerdown(st); in ad7266_postdisable()
85 struct ad7266_state *st = iio_priv(indio_dev); in ad7266_trigger_handler() local
88 ret = spi_read(st->spi, st->data.sample, 4); in ad7266_trigger_handler()
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| H A D | ad4030.c | 75 #define AD4030_REG_IO_MASK_IO2X BIT(1)
83 /* Sequence starting with "1 0 1" to enable reg access */
93 * This accounts for 1 sample per channel plus one s64 for the timestamp,
194 .indexed = 1, \
224 .indexed = 1, \
227 .channel2 = (_idx) * 2 + 1, \
230 .has_ext_scan_type = 1, \
236 1, 2, 4, 8, 16, 32, 64, 128,
241 static int ad4030_enter_config_mode(struct ad4030_state *st) in ad4030_enter_config_mode() argument
243 st->tx_data[0] = AD4030_REG_ACCESS; in ad4030_enter_config_mode()
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| H A D | ad7280a.c | 46 #define AD7280A_CTRL_HB_CONV_INPUT_6CELL_AUX1_3_5 1
51 #define AD7280A_CTRL_HB_CONV_RREAD_6CELL_AUX1_3_5 1
56 #define AD7280A_CTRL_HB_CONV_START_CS 1
57 #define AD7280A_CTRL_HB_CONV_AVG_MSK GENMASK(2, 1)
59 #define AD7280A_CTRL_HB_CONV_AVG_2 1
68 #define AD7280A_CTRL_LB_ACQ_TIME_800ns 1
74 #define AD7280A_CTRL_LB_INC_DEV_ADDR_MSK BIT(1)
85 #define AD7280A_ALERT_REMOVE_AUX3_AUX5 BIT(1)
125 #define AD7280A_MAX_SPI_CLK_HZ 700000 /* < 1MHz */
130 AD7280A_CELL_VOLTAGE_1_REG + 1)
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| H A D | ti-ads7950.c | 54 (((val) >> (dec)) & ((1 << (bits)) - 1))
60 #define TI_ADS7950_MAN_CMD_SETTINGS(st) \ argument
61 (TI_ADS7950_MAN_CMD(TI_ADS7950_CR_WRITE | st->cmd_settings_bitmask))
63 #define TI_ADS7950_GPIO_CMD_SETTINGS(st) \ argument
64 (TI_ADS7950_GPIO_CMD(st->gpio_cmd_settings_bitmask))
139 .indexed = 1, \
158 TI_ADS7950_V_CHAN(1, bits), \
167 TI_ADS7950_V_CHAN(1, bits), \
180 TI_ADS7950_V_CHAN(1, bits), \
197 TI_ADS7950_V_CHAN(1, bits), \
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| /linux/drivers/gpu/drm/etnaviv/ |
| H A D | etnaviv_cmd_parser.c | 26 #define ST(start, num) { (start) >> 2, (num) } macro
28 ST(0x1200, 1),
29 ST(0x1228, 1),
30 ST(0x1238, 1),
31 ST(0x1284, 1),
32 ST(0x128c, 1),
33 ST(0x1304, 1),
34 ST(0x1310, 1),
35 ST(0x1318, 1),
36 ST(0x12800, 4),
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| /linux/drivers/staging/iio/frequency/ |
| H A D | ad9832.c | 123 (u64)((u64)1L << AD9832_FREQ_BITS); in ad9832_calc_freqreg()
128 static int ad9832_write_frequency(struct ad9832_state *st, in ad9832_write_frequency() argument
136 clk_freq = clk_get_rate(st->mclk); in ad9832_write_frequency()
147 st->freq_data[i] = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, freq_cmd) | in ad9832_write_frequency()
152 return spi_sync(st->spi, &st->freq_msg); in ad9832_write_frequency()
155 static int ad9832_write_phase(struct ad9832_state *st, in ad9832_write_phase() argument
169 st->phase_data[i] = cpu_to_be16(FIELD_PREP(AD9832_CMD_MSK, phase_cmd) | in ad9832_write_phase()
174 return spi_sync(st->spi, &st->phase_msg); in ad9832_write_phase()
181 struct ad9832_state *st = iio_priv(indio_dev); in ad9832_write() local
190 mutex_lock(&st->lock); in ad9832_write()
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| H A D | ad9834.c | 49 #define AD9834_MODE BIT(1)
54 #define RES_MASK(bits) (BIT(bits) - 1)
109 static int ad9834_write_frequency(struct ad9834_state *st, in ad9834_write_frequency() argument
115 clk_freq = clk_get_rate(st->mclk); in ad9834_write_frequency()
122 st->freq_data[0] = cpu_to_be16(addr | (regval & in ad9834_write_frequency()
124 st->freq_data[1] = cpu_to_be16(addr | ((regval >> in ad9834_write_frequency()
128 return spi_sync(st->spi, &st->freq_msg); in ad9834_write_frequency()
131 static int ad9834_write_phase(struct ad9834_state *st, in ad9834_write_phase() argument
136 st->data = cpu_to_be16(addr | phase); in ad9834_write_phase()
138 return spi_sync(st->spi, &st->msg); in ad9834_write_phase()
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| /linux/drivers/macintosh/ |
| H A D | windfarm_pid.c | 25 void wf_pid_init(struct wf_pid_state *st, struct wf_pid_param *param) in wf_pid_init() argument
27 memset(st, 0, sizeof(struct wf_pid_state)); in wf_pid_init()
28 st->param = *param; in wf_pid_init()
29 st->first = 1; in wf_pid_init()
33 s32 wf_pid_run(struct wf_pid_state *st, s32 new_sample) in wf_pid_run() argument
37 int i, hlen = st->param.history_len; in wf_pid_run()
40 error = new_sample - st->param.itarget; in wf_pid_run()
43 if (st->first) { in wf_pid_run()
45 st->samples[i] = new_sample; in wf_pid_run()
46 st->errors[i] = error; in wf_pid_run()
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| /linux/crypto/ |
| H A D | aegis128-neon-inner.c | 42 static void aegis128_save_state_neon(struct aegis128_state st, void *state) in aegis128_save_state_neon() argument
44 vst1q_u8(state, st.v[0]); in aegis128_save_state_neon()
45 vst1q_u8(state + 16, st.v[1]); in aegis128_save_state_neon()
46 vst1q_u8(state + 32, st.v[2]); in aegis128_save_state_neon()
47 vst1q_u8(state + 48, st.v[3]); in aegis128_save_state_neon()
48 vst1q_u8(state + 64, st.v[4]); in aegis128_save_state_neon()
57 if (!__builtin_expect(aegis128_have_aes_insn, 1)) { in aegis_aes_round()
88 w = (v << 1) ^ (uint8x16_t)(((int8x16_t)v >> 7) & 0x1b); in aegis_aes_round()
107 struct aegis128_state aegis128_update_neon(struct aegis128_state st, in aegis128_update_neon() argument
110 m ^= aegis_aes_round(st.v[4]); in aegis128_update_neon()
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| /linux/drivers/iio/accel/ |
| H A D | sca3000.c | 34 #define SCA3000_EEPROM_CS_ERROR BIT(1)
63 * (approx 1 - 25Hz) and then a programmable threshold used to trigger
77 #define SCA3000_INT_STATUS_X_TRIGGER BIT(1)
109 #define SCA3000_MD_CTRL_OR_X BIT(1)
182 * @option_mode_1_freq: option mode 1 sampling frequency
277 static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val) in sca3000_write_reg() argument
279 st->tx[0] = SCA3000_WRITE_REG(address); in sca3000_write_reg()
280 st->tx[1] = val; in sca3000_write_reg()
281 return spi_write(st->us, st->tx, 2); in sca3000_write_reg()
284 static int sca3000_read_data_short(struct sca3000_state *st, in sca3000_read_data_short() argument
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| /linux/drivers/iio/common/hid-sensors/ |
| H A D | hid-sensor-attributes.c | 22 HID_USAGE_SENSOR_UNITS_METERS_PER_SEC_SQRD, 1, 0},
28 HID_USAGE_SENSOR_UNITS_METERS_PER_SEC_SQRD, 1, 0},
34 HID_USAGE_SENSOR_UNITS_RADIANS_PER_SECOND, 1, 0},
39 {HID_USAGE_SENSOR_COMPASS_3D, HID_USAGE_SENSOR_UNITS_GAUSS, 1, 0},
45 HID_USAGE_SENSOR_UNITS_RADIANS, 1, 0},
47 {HID_USAGE_SENSOR_ALS, 0, 1, 0},
48 {HID_USAGE_SENSOR_ALS, HID_USAGE_SENSOR_UNITS_LUX, 1, 0},
57 {HID_USAGE_SENSOR_DEVICE_ORIENTATION, 0, 1, 0},
59 {HID_USAGE_SENSOR_RELATIVE_ORIENTATION, 0, 1, 0},
61 {HID_USAGE_SENSOR_GEOMAGNETIC_ORIENTATION, 0, 1, 0},
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| /linux/drivers/iio/frequency/ |
| H A D | adf4377.c | 32 #define ADF4377_0000_LSB_FIRST_MSK BIT(1)
158 #define ADF4377_0019_PD_ADC_MSK BIT(1)
174 #define ADF4377_001A_PD_CLKOUT1_MSK BIT(1)
202 #define ADF4377_001D_CP_DOWN_MSK BIT(1)
286 #define ADF4377_002E_EN_ADC_MSK BIT(1)
294 #define ADF4377_002F_DCLK_DIV1_MSK GENMASK(1, 0)
330 #define ADF4377_003D_O_VCO_BIAS_MSK BIT(1)
353 #define ADF4377_0049_FSM_BUSY_MSK BIT(1)
357 #define ADF4377_004B_VCO_CORE_MSK GENMASK(1, 0)
479 struct adf4377_state *st = iio_priv(indio_dev); in adf4377_reg_access() local
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| H A D | adrf6780.c | 52 #define ADRF6780_LO_EN_MSK BIT(1)
66 #define ADRF6780_ADC_EN_MSK BIT(1)
91 static int __adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg, in __adrf6780_spi_read() argument
97 st->data[0] = 0x80 | (reg << 1); in __adrf6780_spi_read()
98 st->data[1] = 0x0; in __adrf6780_spi_read()
99 st->data[2] = 0x0; in __adrf6780_spi_read()
101 t.rx_buf = &st->data[0]; in __adrf6780_spi_read()
102 t.tx_buf = &st->data[0]; in __adrf6780_spi_read()
105 ret = spi_sync_transfer(st->spi, &t, 1); in __adrf6780_spi_read()
109 *val = (get_unaligned_be24(&st->data[0]) >> 1) & GENMASK(15, 0); in __adrf6780_spi_read()
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| /linux/drivers/iio/resolver/ |
| H A D | ad2s1210.c | 17 * LOT Low Threshold [1] | 0x8E | events/in_angl1_thresh_rising_hysteresis
27 * [1]: The value written to the LOT low register is high value minus the
76 #define AD2S1210_SET_RES GENMASK(1, 0)
85 #define AD2S1210_FAULT_PHASE BIT(1)
119 /* Threshold voltage registers have 1 LSB == 38 mV */
176 static int ad2s1210_set_mode(struct ad2s1210_state *st, enum ad2s1210_mode mode) in ad2s1210_set_mode() argument
178 struct gpio_descs *gpios = st->mode_gpios; in ad2s1210_set_mode()
182 return mode == st->fixed_mode ? 0 : -EOPNOTSUPP; in ad2s1210_set_mode()
198 struct ad2s1210_state *st = context; in ad2s1210_regmap_reg_write() local
201 .len = 1, in ad2s1210_regmap_reg_write()
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| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | st,stmpe.yaml | 4 $id: http://devicetree.org/schemas/mfd/st,stmpe.yaml#
23 - st,stmpe601
24 - st,stmpe801
25 - st,stmpe811
26 - st,stmpe1600
27 - st,stmpe1601
28 - st,stmpe2401
29 - st,stmpe2403
32 maxItems: 1
35 maxItems: 1
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| /linux/drivers/staging/iio/impedance-analyzer/ |
| H A D | ad5933.c | 26 #define AD5933_REG_CONTROL_HB 0x80 /* R/W, 1 byte */
27 #define AD5933_REG_CONTROL_LB 0x81 /* R/W, 1 byte */
32 #define AD5933_REG_STATUS 0x8F /* R, 1 byte */
46 #define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
47 #define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
48 #define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
49 #define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
50 #define AD5933_CTRL_RANGE(x) ((x) << 1)
62 #define AD5933_STAT_DATA_VALID (0x1 << 1)
75 #define AD5933_OUT_RANGE 1
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