Searched +full:1 +full:c600000 (Results 1 – 7 of 7) sorted by relevance
30 maxItems: 133 maxItems: 140 maxItems: 143 maxItems: 158 port@1:71 0 - For 1 lane enabled in IP.72 0 1 - For 2 lanes enabled in IP.73 0 1 2 3 - For 4 lanes enabled in IP.74 minItems: 181 - port@1[all …]
31 #phy-cells = <1>;39 phy-id = <1>;40 #phy-cells = <1>;49 #phy-cells = <1>;85 num-lanes = <1>;86 phys = <&miphy0 1>;102 num-lanes = <1>;103 phys = <&miphy1 1>;119 num-lanes = <1>;120 phys = <&miphy2 1>;[all …]
78 adsp_mem: memory@8c600000 {84 sw_edp_1p2: edp-1p2-regulator {382 #address-cells = <1>;392 #address-cells = <1>;403 port@1 {404 reg = <1>;420 connector@1 {422 reg = <1>;432 #address-cells = <1>;437 #address-cells = <1>;[all …]
153 clocks = <&cpufreq_hw 1>;160 qcom,freq-domain = <&cpufreq_hw 1>;176 clocks = <&cpufreq_hw 1>;183 qcom,freq-domain = <&cpufreq_hw 1>;199 clocks = <&cpufreq_hw 1>;206 qcom,freq-domain = <&cpufreq_hw 1>;222 clocks = <&cpufreq_hw 1>;229 qcom,freq-domain = <&cpufreq_hw 1>;290 big_cpu_sleep_0: cpu-sleep-1-0 {663 pil_nsp1_mem: cdsp1-region@8c600000 {[all …]
21 #define SPEAR1310_CLCD_SYNT_CLK_MASK 143 #define SPEAR1310_GPT_APB_VAL 144 #define SPEAR1310_GPT_CLK_MASK 150 #define SPEAR1310_UART_CLK_OSC24_VAL 156 #define SPEAR1310_AUX_CLK_SYNT_VAL 159 #define SPEAR1310_C3_CLK_MASK 160 #define SPEAR1310_C3_CLK_SHIFT 165 #define SPEAR1310_GMAC_PHY_CLK_MASK 168 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 183 #define SPEAR1310_I2S_REF_SEL_MASK 1[all …]
57 nvidia,int-threshold = <1>;58 #timestamp-cells = <1>;97 #dma-cells = <1>;99 iommu-map = <1 &smmu1 0x801 31>;204 #dma-cells = <1>;238 #address-cells = <1>;249 i2s1_port: port@1 {250 reg = <1>;273 #address-cells = <1>;284 i2s2_port: port@1 {[all …]
49 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,219 #dma-cells = <1>;266 #address-cells = <1>;277 i2s1_port: port@1 {278 reg = <1>;302 #address-cells = <1>;313 i2s2_port: port@1 {314 reg = <1>;338 #address-cells = <1>;349 i2s3_port: port@1 {[all …]