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/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,dp.yaml30 maxItems: 1
33 maxItems: 1
40 maxItems: 1
43 maxItems: 1
58 port@1:
71 0 - For 1 lane enabled in IP.
72 0 1 - For 2 lanes enabled in IP.
73 0 1 2 3 - For 4 lanes enabled in IP.
74 minItems: 1
81 - port@1
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/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi31 #phy-cells = <1>;
39 phy-id = <1>;
40 #phy-cells = <1>;
49 #phy-cells = <1>;
85 num-lanes = <1>;
86 phys = <&miphy0 1>;
102 num-lanes = <1>;
103 phys = <&miphy1 1>;
119 num-lanes = <1>;
120 phys = <&miphy2 1>;
[all …]
/linux/drivers/clk/spear/
H A Dspear1310_clock.c21 #define SPEAR1310_CLCD_SYNT_CLK_MASK 1
43 #define SPEAR1310_GPT_APB_VAL 1
44 #define SPEAR1310_GPT_CLK_MASK 1
50 #define SPEAR1310_UART_CLK_OSC24_VAL 1
56 #define SPEAR1310_AUX_CLK_SYNT_VAL 1
59 #define SPEAR1310_C3_CLK_MASK 1
60 #define SPEAR1310_C3_CLK_SHIFT 1
65 #define SPEAR1310_GMAC_PHY_CLK_MASK 1
68 #define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT 1
83 #define SPEAR1310_I2S_REF_SEL_MASK 1
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm6125.dtsi55 cpu1: cpu@1 {
165 #reset-cells = <1>;
201 #clock-cells = <1>;
208 #power-domain-cells = <1>;
377 #address-cells = <1>;
378 #size-cells = <1>;
385 #hwlock-cells = <1>;
669 #clock-cells = <1>;
670 #reset-cells = <1>;
671 #power-domain-cells = <1>;
[all …]
H A Dsm6115.dtsi66 cpu1: cpu@1 {
112 clocks = <&cpufreq_hw 1>;
117 qcom,freq-domain = <&cpufreq_hw 1>;
131 clocks = <&cpufreq_hw 1>;
136 qcom,freq-domain = <&cpufreq_hw 1>;
145 clocks = <&cpufreq_hw 1>;
150 qcom,freq-domain = <&cpufreq_hw 1>;
159 clocks = <&cpufreq_hw 1>;
164 qcom,freq-domain = <&cpufreq_hw 1>;
220 big_cpu_sleep_0: cpu-sleep-1-0 {
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi162 snps,write-requests = <1>;
207 #dma-cells = <1>;
548 dmas = <&adma 1>, <&adma 1>,
610 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
641 #dma-cells = <1>;
687 #interconnect-cells = <1>;
731 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
807 #address-cells = <1>;
834 #address-cells = <1>;
850 #address-cells = <1>;
[all …]
H A Dtegra234.dtsi49 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
170 #dma-cells = <1>;
217 #address-cells = <1>;
228 i2s1_port: port@1 {
229 reg = <1>;
253 #address-cells = <1>;
264 i2s2_port: port@1 {
265 reg = <1>;
289 #address-cells = <1>;
300 i2s3_port: port@1 {
[all …]